Cirrus-logic EP73xx Manual do Utilizador descarregar pdf (Página 69)

EP7309/11/12 User’s Manual - DS508UM4 5-9

System Registers

Refer to the Expansion Bus Controller chapterfor explicit details

on programmed wait states at different bus frequencies.

DAISEL: When set, selects the DAI interface. When cleared, selects the SSI

interface.

ADCCKNSEN:When set, ADC configuration data is transmitted on

ADCOUT

at the rising edge of the ADCCLK, and data is read back on the

falling edge of the

ADCIN pin. When clear, the opposite edges are

used.

VERSN: These read-only bits will always read ‘000’ on the EP73xx.

Reserved-0:This bit must always be set to zero.

128Fs: DAI Frame size select. When set, the DAI will operate on 128-bit

frames. When cleared, the DAI uses 64-bit frames.

ENPD67: Port Dbits 6 and 7 enable.When this bit is set, thesebitson Port D

are enabled as GPIOs. When cleared, the pins assigned

PD[6] and

PD[7] are used as SDQM[0] and SDQM[1] respectively for the

SDRAM interface. ENPD67 must be clear in order to properly use

the SDRAM interface.

System Flag Register 1 (SYSFLG1)

Address: 0x8000.0140, Read Only

Definition: The SYSFLG1 system flag register is a 32-bit read only register. It

providesinformationregarding thestatusofthe CPU and associated

peripherals.

Table 5-4: ARM720T Clock Speed Settings

CLKCTL[1-0]

Value

Processor

Frequency

Memory Bus

Frequency

Wait State

Scaling

00 18.432 MHz 18.432 MHz 1

01 36.864 MHz 36.864 MHz 2

10 49.152 MHz 36.864 MHz 2

11 73.728 MHz 36.864 MHz 2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VERID ID BOOTBI

BOOTBI

SSIBUS

CTXFF CRXFE UTXFF1 URXFE1 RTCDIV

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CLDFLG PFFLG RSTFLG NBFLG UBUSY

DCD DSR CTS DID WUON WUDR DCDET MCDR

1 2 ... 64 65 66 67 68 69 70 71 72 73 74 ... 157 158

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