Cirrus-logic EP73xx Manual do Utilizador descarregar pdf (Página 32)

2-6 EP7309/11/12 User’s Manual - DS508UM4

CPU Core

Cache is direct-mapped. The copy of the address or data is stored along with an

address tag that is compared with the location in system memory. Cache is also write-

through and uses a replacement algorithm to select which of the four possible

locations will be overwritten in the case of a cache miss.

Write Buffer

The write buffer holds four addresses and eight data words.The MMU defines which

addresses are bufferable. Each address can be associated with any number of data

words. Data words are written to sequential memory starting at that address.

Thewrite buffer becomes fullwhen allfour addresses areused or alleight data words

are used. The processor can write into the write buffer at fast cache speed and

continue executing instructionsstored in cache while the write buffer stores data to

external memory at the current memory bus speed. If there is a memory fault

generated by a buffered write, the system will not be able to recoverfrom it since the

processor state is not recoverable.

Figure 2-2. ARM720T Cache Organization

encode

Data RAM

2048 x 32-bit

word

tag RAM

128 entry

tag RAM

128 entry

tag RAM

128 entry

tag RAM

128 entry

=? =? =? =?

31 11 10 43210

[1:0]

[8:2]

[10:9]

[10:0]

hit data

byte

addresses

virtual address

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 157 158

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Cirrus-logic EP73xx Manual do Utilizador Página 32