Cirrus-logic EP73xx Manual do Utilizador descarregar pdf (Página 138)

16-14 EP7309/11/12 User’s Manual - DS508UM4

DAI/CODEC/SSI2

RCTM:

The Left Channel Sample Receive FIFO interrupt mask (LCRM) bit is used to mask or

enable the Left Channel Receive FIFO service request interrupt. When LCRM = 0, the

interrupt is masked and the state of the left channel sample receive FIFO service

request (LCRS) bit within the DAI status register is ignored by the interrupt

controller. When LCRM = 1, the interrupt is enabled and whenever LCRS is set (one)

an interrupt request is made to the interrupt controller. Note that programming

LCRM = 0 does not affect the current state of LCRS or the Left Channel Receive FIFO

logic’s ability to set and clear LCRS, it only blocks the generation of the interrupt

request.

RCRM:

The Right Channel Receive FIFO interrupt mask (RCRM) bit is used to mask or

enable the Right Channel Receive FIFO service request interrupt. When RCRM = 0,

the interrupt is masked and the state of the Right Channel Receive FIFO service

request (RCRS) bit within the DAI status register is ignored by the interrupt

controller. WhenRCRM=1,theinterruptisenabled,and whenever RCRSisset(one),

an interrupt request is made to the interrupt controller. Note that programming

RCRM = 0 does not affect the current state of RCRS orthe Right Channel Receive

FIFO logic’s ability to set and clear RCRS, for it only blocks the generation of the

interrupt request.

DAI Data Register 0 (DAIDR0)

Address: 0x8000.2040, Read / Write

Bit Descriptions:

[0:15]: Bottom Right Receive and Top Right Transmit FIFO. Data is filed

and extracted from the Right Channel FIFOs usingthis register.

Data Read: Data received by the DAI machine from external hardware and is

placed the top of the receive FIFO and shifted down for each new

entry into the FIFO until it reaches the last empty location within

the FIFO. Data is removed from the FIFO by a system software

read from the bottom of the FIFO. The bottom value is the

replaced bythe next valueas all information with the FIFO is then

shifted down one location.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bottom Right Channel Receive FIFO / Top Right Channel Transmit FIFO

1 2 ... 133 134 135 136 137 138 139 140 141 142 143 ... 157 158

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Cirrus-logic EP73xx Manual do Utilizador Página 138