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EP7309/11/12 User’s Manual - DS508UM4 4-1

Chapter 4

4Interrupt Controller

Introduction

Like most modern microprocessors, the EP73xx contains an interrupt controller to

manage both external and internal exceptions. When an expected or unexpected

event arises during the execution of a program (i.e. interrupt or memory fault) an

exception is generated. If more than one exception occurs at the same time, a fixed

priority system determines the order in which they are handled.

Features

• Interrupt requests received from 22 different sources

• Standard (IRQ) and Fast (FIQ) interrupt types

• Interrupts can be used to wake the CPU from IDLE or STANDBY

Interrupt Register List

Table 4-1: Interrupt Registers

Address Name Type Size Description Page

0x8000.0240 INTSR1 RO 32 Interrupt Status page 4-8

0x8000.1240 INTSR2 R/W 32 Interrupt Status page 4-11

0x8000.2240 INTSR3 R/W 32 Interrupt Status page 4-12

0x8000.0280 INTMR1 R/W 32 Interrupt Mask page 4-10

0x8000.1280 INTMR2 R/W 32 Interrupt Mask page 4-12

0x8000.2280 INTMR3 R/W 32 Interrupt Mask page 4-13

0x8000.0600 BLEOI R/W --- Battery Low EOI page 4-13

0x8000.0640 MCEOI R/W --- Media Change EOI page 4-13

0x8000.0680 TEOI R/W --- Tick Watchdog EOI page 4-13

0x8000.06C0 TC1EOI R/W --- TC1 EOI page 4-13

0x8000.0700 TC2EOI R/W --- TC2 EOI page 4-14

0x8000.0740 RTCEOI R/W --- RTC Match EOI page 4-14

0x8000.0780 UMSEOI R/W --- UART1 Modem EOI page 4-14

1 2 ... 42 43 44 45 46 47 48 49 50 51 52 ... 157 158

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