manuais Cirrus Logic EP73xx

Cirrus logic EP73xx Manual do Utilizador (158 páginas)

Marca: Cirrus-logic | Categoria: Hardware | Tamanho: 1.80 MB |

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Índice

EP73xx User’s Guide

1

1Contents

4

Chapter 5. System Registers

5

Chapter 6. Processor Support

6

Chapter 7. SDRAM Controller

6

Chapter 9. LCD Interface

6

Appendix A. Boot Code

8

Contents

9

List of Figures

10

List of Tables

12

Chapter 1

15

1Introduction

15

Overview

15

Memory Map and Register List

16

Internal Register Map

17

Pin Description

20

External Signal Functions

21

Output Bi-Directional Pins

24

Block Diagrams

25

References

26

Chapter 2

27

2CPU Core

27

Programming Register List

27

Programming Examples

28

CPU Core

29

Write Buffer

32

CPU Register Definitions

33

User FIQ IRQ SVC Undef Abort

34

CPU Clocks

35

On-Chip PLL

36

PLL Register Descriptions

37

CPU State Control

38

Idle State

39

Power Up Sequence

40

Table 3-1: Timer Registers

43

Timer Register Descriptions

45

Chapter 4

47

4Interrupt Controller

47

Interrupt Register List

47

Interrupt Operation

50

Interrupt Listing

51

Operating State

52

Standby State

53

Interrupt Controller

54

End-Of-Interrupt Locations

59

Chapter 5

61

5System Registers

61

System Register List

62

MaverickKey

64

Unique-ID

64

BUZ output reflects

65

EXPCLK is

66

System Registers

68

0032-bit

71

1016-bit

71

11Reserved

71

CLKSEL (PE[2])input,latched

72

Chapter 6

75

6Processor Support

75

Internal Boot Mode

76

External Boot Mode

76

CS0 and the

77

Endianess

78

Endian Byte Addressing

79

Processor Support

80

Chapter 7

81

7SDRAM Controller

81

SDRAM Register List

81

SDRAM Register Descriptions

83

SDRAM Controller

84

SRAM/Expansion Bus Controller

89

Chapter 9

91

9LCD Interface

91

LCD Register List

91

LCD DMA Controller

93

Gray Scale

94

4 Bits per pixel

95

2 Bits per pixel

95

1 Bit per pixel

95

Hardware Interface

96

Color LCDs

96

LCD Register Descriptions

97

(PALMSW)

98

FBADDR)

99

LCD Interface

100

Operational Overview

102

Keyboard Interface

103

Chapter 11

105

11General Purpose I/O (GPIO)

105

Introduction

105

Features

105

Programming Example

106

Register Descriptions

106

Chapter 12

107

12PWM Interface

107

Block Diagram

107

PWM Register Descriptions

109

PWM Interface

110

PD0 / LEDFLSH)tobetoggledata

111

Register Definitions

112

Chapter 14

113

14JTAG Interface

113

Boundary Scan

114

Debug Modes

115

Debug/ICE Test Mode

116

Hi-Z (System) Test Mode

116

JTAG Interface

117

ADCCLK)

121

Bit Descriptions:

122

(SYNCIO[6:0])

123

SSI Port

124

Chapter 16

125

16DAI/CODEC/SSI2

125

DAI/CODEC/SSI2 Register List

126

DAI Interface

128

DAI Clock Generation

129

Master/Slave SSI2 Interface

131

Read Back of Residual Data

132

CODEC Sound Interface

134

DAI Registers

135

DAI Control Register (DAIR)

136

Full Bit Descriptions

137

DAI Data Register 0 (DAIDR0)

138

DAI Data Register 1 (DAIDR1)

139

DAI Data Register 2 (DAIDR2)

140

DAI Status Register (DAISR)

140

DAI/CODEC/SSI2

141

SSI2 Registers

144

CODEC Register

144

SIR Encoder

150

UART and SIR Encoder

153

WRDLEN Word Length

153

Appendix A

155

ABoot Code

155

Boot Code

156

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