Cirrus-logic EP93xx Manual do Utilizador descarregar pdf (Página 774)

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27-4 DS785UM1

IDE Interface

EP93xx User’s Guide

For a Write Operation.

1. Write out the register value.

2. Delay as follows, based on the PIO mode.

PIO Mode 0 - Delay for 70 ns.

PIO Mode 1 - Delay for 50 ns.

PIO Mode 2 - Delay for 30 ns

PIO Mode 3 - Delay for 30 ns

PIO Mode 4 - Delay for 25 ns

3. Bring DIOWn high.

4. Delay as follows, based on the PIO mode.

PIO Mode 0 - Delay for 290 ns.

PIO Mode 1 - Delay for 290 ns

PIO Mode 2 - Delay for 290 ns

PIO Mode 3 - Delay for 80 ns

PIO Mode 4 - Delay for 70 ns

5. Bring DIOWn low.

6. Delay as follows, based on the PIO mode before the next read or write can occur.

PIO Mode 0 - 240 ns.

PIO Mode 1 - 50 ns

PIO Mode 2 - 20 ns

PIO Mode 3 - 70 ns

PIO Mode 4 - 25 ns

Minimum total cycle time for the various PIO modes is as follows:

PIO Mode 0 - 600 ns

PIO Mode 1 - 383 ns

PIO Mode 2 - 330 ns

PIO Mode 3 - 180 ns

PIO Mode 4 - 120 ns

You must also setup IDECFG and WST as follows, according to the PIO mode:

PIO Mode 0 - Delay for 30 ns

PIO Mode 1 - Delay for 20 ns

PIO Mode 2 - Delay for 15 ns

PIO Mode 3 - Delay for 10 ns

PIO Mode 4 - Delay for 5 ns

27.2.3 MDMA Operations

For MDMA operations, DMA commands are set up using PIO operations by the host. The

registers IDEMDMADataOut and IDEMDMADataIn act as the 1-deep buffer for write and

read operations respectively. The state machine sets up the necessary signals including the

DMA request to the DMA controller.

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Cirrus-logic EP93xx Manual do Utilizador Página 774

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