Cirrus-logic EP93xx Manual do Utilizador descarregar pdf (Página 39)

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DS785UM1 2-1

Chapter 2

2ARM920T Core and Advanced High-Speed Bus (AHB)

2.1 Introduction

This chapter describes the ARM920T Core and the Advanced High-Speed Bus (AHB).

2.2 Overview: ARM920T Core

The ARM920T is a Harvard architecture core with separate 16 kbyte instruction and data

caches with an 8-word line length. The ARM Core utilizes a five-stage pipeline consisting of

fetch, decode, execute, data memory access, and write stages.

2.2.1 Features

Key features include:

• ARM V4T (32-bit) and Thumb (16-bit compressed) instruction sets

• 32-bit Advanced Micro-Controller Bus Architecture (AMBA)

• 16 kbyte Instruction Cache with lockdown

• 16 kbyte Data Cache (programmable write-through or write-back) with lockdown

• Write Buffer

• MMU for Microsoft Windows CE and Linux operating systems

• Translation Look-aside Buffers (TLB) with 64 Data and 64 Instruction Entries

• Programmable Page Sizes of 64 kbyte, 4 kbyte, and 1 kbyte

• Independent lockdown of TLB Entries

• JTAG Interface for Debug Control

• Co-processor Interface

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Cirrus-logic EP93xx Manual do Utilizador Página 39

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