Cirrus-logic EP93xx Manual do Utilizador descarregar pdf (Página 358)

100

101

9-56 DS785UM1

1/10/100 Mbps Ethernet LAN Controller

EP93xx User’s Guide

Definition:

Receive Miss Count Register

Bit Descriptions:

RSVD: Reserved. Unknown During Read.

RMC: Receive Miss Count. The Receive Miss Count records the

number of frames that pass the destination address filter,

but fail to be received due to lack of bus availability or lack

of receive storage. Frames that are partially stored and

marked as overruns are included in the count. When the

most significant bit of the count is set, an optional interrupt

may be generated. The register is cleared automatically

following a read, writing to the register will have no effect.

RXRuntCnt

Address:

0x8001_0078 - Read Only

Chip Reset:

0x0000_0000

Soft Reset:

0x0000_0000

Definition:

Receive Runt Count Register

Bit Descriptions:

RSVD: Reserved. Unknown During Read.

RRC: Receive Runt Count. The receive runt count records the

total number of runt frames received, including those with

bad CRC. When the most significant bit of the count is set,

an optional interrupt may be generated. The register is

cleared automatically following a read, writing to the

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

1514131211109876543210

RRC

1 2 ... 353 354 355 356 357 358 359 360 361 362 363 ... 823 824

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Cirrus-logic EP93xx Manual do Utilizador Página 358

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