Cirrus-logic EP93xx Manual do Utilizador descarregar pdf (Página 543)

DS785UM1 14-21

UART1 With HDLC and Modem Control Signals

EP93xx User’s Guide

UART Line Control Register Middle.

Bit Descriptions:

RSVD: Reserved. Unknown During Read.

BR: Baud Rate Divisor bits [15:8]. Most significant byte of baud

rate divisor. These bits are cleared to 0 on reset.

UART1LinCtrlLow

0x808C_0010 - Read/Write

UART Line Control Register Low.

Bit Descriptions:

RSVD: Reserved. Unknown During Read.

BR: Baud Rate Divisor bits [7:0]. Least significant byte of baud

rate divisor. These bits are cleared to 0 on reset. The baud

rate divisor is calculated as follows:

Baud rate divisor

BAUDDIV = (F

/ 16 * Baud rate)) – 1

is the UART reference clock frequency. A

baud rate divisor of zero is not allowed and will result in no

data transfer.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

1514131211109876543210

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Cirrus-logic EP93xx Manual do Utilizador Página 543