Cirrus-logic CS6422 Manual do Utilizador descarregar pdf (Página 19)

CS6422

3.5 Register 2

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

RHDet RSThd NseRmp HDly HHold TDSRmp RDSRmp IdlTx 0 1 0 0

00 00 00 00 0 0 0 0

00 0 4

Bits Name Function Word Operation

15-14 RHDet Rx Half-duplex Detection threshold 00*

6 dB

9 dB

12 dB

reserved

13-12 RSThd Rx Suppression Threshold 00*

6 dB

9 dB

12 dB

reserved

11-10 NseRmp Noise estimator Ramp rate 00*

3 dB/s

6 dB/s

12 dB/s

reserved

9-8 HDly half-duplex Holdover Delay 00*

200 ms

100 ms

150 ms

reserved

7 HHold Hold in half-duplex on Howl 0*

disable HHold

enable HHold

6 TDSRmp Tx Double-talk Suppression Ramp rate 0*

slow

normal

5 RDSRmp Rx Double-talk Suppression Ramp rate 0*

slow

normal

4 IdlTx half-duplex Idle return-to-Transmit 0*

disable IdlTx

enable IdlTx

* Denotes reset value

Table 5. Register 2 Bit Definitions

CS6422

DS295F1 19

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 47 48

Features 1
General Description 1
TABLE OF CONTENTS 2
LIST OF FIGURES 4
LIST OF TABLES 4
ABSOLUTE MAXIMUM RATINGS 5
POWER CONSUMPTION 5
ANALOG CHARACTERISTICS (T 5
MICROPHONE AMPLIFIER (T 6
DIGITAL CHARACTERISTICS (T 6
Bit14 Bit2 Bit1 8
Bit0DATA 8
DS295F1 9 9
2. OVERVIEW 10
3. FUNCTIONAL DESCRIPTION 10
3.1 Analog Interface 10
3.1.1 Acoustic Interface 11
3.1.2 Network Interface 12
3.2 Microcontroller Interface 12
3.2.1 Description 12
3.2.2 Register Definitions 13
3.3 Register 0 14
3.3.3 GB - GRADED BETA 15
3.4 Register 1 17
3.5 Register 2 19
3.6 Register 3 22
3.7 Register 4 24
3.8 Register 5 26
3.9 Reset 29
3.9.1 Cold Reset 29
3.9.2 Warm Reset 29
3.9.3 Reset Timer 29
3.10 Clocking 29
3.11 Power Supply 30
3.11.1 Power Down Mode 30
3.11.2 Noise and Grounding 30
4. DESIGN CONSIDERATIONS 32
4.1.1 Full-Duplex Mode 32
4.1.1.1 Theory of Operation 32
4.1.1.2 Adaptive Filter 33
4.1.1.2.1 Pre-Emphasis 33
4.1.1.2.2 Graded Beta 34
4.1.1.3 Update Control 34
4.1.1.4 Speech Detection 34
4.1.2 Half-Duplex Mode 35
4.1.3 AGC 35
4.1.4 Suppression 36
4.1.4.1 Transmit Suppression 37
4.1.4.2 Receive Suppression 37
4.1.4.4 Noise Guard 38
4.2 Circuit Design 38
4.2.1.1 Analog Interface 38
4.2.3 Layout Considerations 39
4.3 System Design 39
4.3.1 Gain Structure 39
4.3.2 Testing Issues 40
4.3.2.1 ERLE 40
4.3.2.2 Convergence Time 41
4.3.2.3 Half-Duplex Switching 41
5. PIN DESCRIPTIONS 42
Miscellaneous 44
NC1 - No Connect, Pin 9 44
NC2 - No Connect, Pin 10 44
NC3 - No Connect, Pin 11 44
NC4 - No Connect, Pin 12 44
6. GLOSSARY 45
7. PACKAGE DIMENSIONS 47
ORDERING INFORMATION 48
REVISION HISTORY 48

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