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AN339

CS8416 Delivers Performance Gains Over CS8413/14

Jonathan Schwartz

1. INTRODUCTION

The CS8413/14 S/PDIF receivers have long held a position of respect as the industry-favored receivers for recov-

ered clock quality. As of early 2009, an upcoming end-of-life of these products has many system designers wonder-

ing what their next move will be, and where they’ll go to get the level of performance they’ve become accustomed

to. Others simply need 192 kHz support, which the CS8413/14 does not provide.

Satisfying both of these requirements, Cirrus Logic offers the

CS8416 S/PDIF receiver with new features and lower recovered

clock jitter than the CS8413/14.

When the CS8416 was first released in 2002, it used a phase de-

tector scheme that resulted in higher recovered clock jitter com-

pared to the CS8413/14. To improve on its performance and follow

in the tradition of the CS8413/14, a new phase detector option was

added to the CS8416 in 2004. This new option offers even lower

recovered clock jitter than the CS8413/14 and results in measur-

ably improved audio performance as shown in Figure 1.

This application note details how the CS8416 improves upon the

performance of the CS8413/14. A summary of important functional

differences and detailed jitter and audio performance measure-

ments are included to clearly demonstrate the improvements that

can be expected when transitioning to the CS8416.

2. SUMMARY OF IMPROVEMENTS

Many improvements were made in the generational leap from the CS8413/14 to the CS8416. For reference, some

of the high-level improvements are summarized in the table below. For more information, please refer to each de-

vice’s datasheet.

Notes: 1. Values listed are from experiment results. See Section 5

2. PDUR=1. See Section 3

Parameter CS8413/14 CS8416

Unit

Maximum Sample Rate 96 192 kHz

Baseband Jitter (Note 1) 158.5 122.6 (Note 2) ps

Logic Supply Voltage Range 5 3.3 - 5 V

Power Supply Consumption 175 47.5 mW

Back-up System Clock During Receiver Error None OMCK pin -

Receiver Input Pins 1 8 in SW Mode, 4 in HW Mode -

Dedicated Reset Pin None Yes -

Control Port Protocol Parallel Port, CS8413 Only I²C and SPI -

Table 1. Summary of CS8416 Improvements

-110

-90

-108

-106

-104

-102

-100

-98

-96

-94

-92

20 20k50 100 200 500 1k 2k 5k 10k

Figure 1. DAC THD+N

CS8414

CS8416

JUL '09

AN339REV1

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Página 1 - 2. SUMMARY OF IMPROVEMENTS

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AN339AN339REV110 AN339REV18. CONCLUSIONThe CS8416 offers many improvements and features beyond those of the CS8413/14. One of the CS8416’s primaryimpr

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AN339AN339REV1AN339REV1 11on the CDB4398 for all measurements sourced by the CS8416. Refer to the CDB4398 and CDB8416 datasheets for more information

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AN339AN339REV112 AN339REV19.2.1 Test ConditionsFor all tests, unless otherwise stated: CS4398 VA = VREF = VD = VLS = VLC = 5 V; PCM data is 24 bitI2S

Página 5

AN339AN339REV12 AN339REV1Beyond those listed in the table, several other notable enhancements are available in the CS8416:There are a number of other

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AN339AN339REV1AN339REV1 34. CS8413/14 AND CS8416 CLOCK RECOVERY COMPAREDThe primary difference between the CS8413/14 and CS8416 PLLs is found in the i

Página 7

AN339AN339REV14 AN339REV1Each receiver, including both of the CS8416 phase detec-tor update modes, was tested with input S/PDIF samplerates at common

Página 8

AN339AN339REV1AN339REV1 5The measurements show the CS8416 has less basebandjitter than the CS8414 when PDUR = 1. While the plotsalso indicate that the

Página 9

AN339AN339REV16 AN339REV1 -130-60-125-120-115-110-105-100-95-90-85-80-75-70-65dBr A20 20k50 100 200 500 1k 2k 5k 10kHzCS8414CS8416 PDUR=0CS8416 PDUR=1

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AN339AN339REV1AN339REV1 76.2 Full-Scale FFTsFFTs of the 997 Hz and 18 kHz test cases are provided below. These show the differences in the tonal andno

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AN339AN339REV18 AN339REV16.3 Dynamic Range MeasurementsAs discussed in section 5.2 of AES-12id-2006, jitter outside of the baseband frequency range ca

Página 12

AN339AN339REV1AN339REV1 97. JITTER MEASUREMENT TO DAC THD+N CORRELATIONThe results presented in Section 5 show that the amount of baseband jitter pres

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