Cirrus-logic CS8415A Manual do Utilizador

Copyright © Cirrus Logic, Inc. 2005(All Rights Reserved)http://www.cirrus.com96 kHz Digital Audio Interface ReceiverFeatures! Complete EIAJ CP1201, IE

10 DS470F4CS8415ASWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE(Note 15), Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.15. I²C protocol is su

DS470F4 11CS8415A2. TYPICAL CONNECTION DIAGRAMRXP0RXN0AES3/SPDIFSourcesClock Control RMCKHardwareControlRSTRERREMPH3-wire SerialAudio InputDeviceOLRCK

12 DS470F4CS8415A3. GENERAL DESCRIPTIONThe CS8415A is a monolithic CMOS device which receives and decodes audio data according to the AES3, IEC60958,

DS470F4 13CS8415A4. SERIAL AUDIO OUTPUT PORTA 3-wire serial audio output port is provided. The port can be adjusted to suit the attached device settin

14 DS470F4CS8415Awhen repeated or dropped samples occur. The CS8415A allows immediate mute of the serial audio output port audio data by the MUTESAO b

DS470F4 15CS8415A5. AES3 RECEIVERThe CS8415A includes an AES3 digital audio receiver. A comprehensive buffering scheme provides read access to the cha

16 DS470F4CS8415Apulse on RERR, invoke the occurrence of a RERR interrupt, and affect the current audio sample accordingto the status of the HOLD bits

DS470F4 17CS8415A5.8 Mono Mode OperationAn AES3 stream may be used in more than one way to transmit 96 kHz sample rate data. One method isto double th

18 DS470F4CS8415A6. CONTROL PORT DESCRIPTION AND TIMINGThe control port is used to access the registers, allowing the CS8415A to be configured for the

DS470F4 19CS8415A6.2 I²C ModeIn I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, withthe clock

2 DS470F4CS8415AORDERING INFORMATIONProduct Description Package GradeTemp Range Pb-Free Container Order NumberCS8415A96 kHz Digital Audio Interface Re

20 DS470F4CS8415A7. CONTROL PORT REGISTER SUMMARY7.1 Memory Address Pointer (MAP)INCR - Auto Increment Address Control BitDefault = ‘0’0 - Disabled1 -

DS470F4 21CS8415A8. CONTROL PORT REGISTER BIT DEFINITIONS8.1 Control 1 (01h) SWCLK - Controls output of OMCK on RMCK when PLL loses lockDefault = ‘0

22 DS470F4CS8415AMUX2:0 - 7:1 S/PDIF Input Multiplexer Select Line ControlDefault = ‘000’000 - RXP0001 - RXP1010 - RXP2011 - RXP3100 - RXP4101 - RXP51

DS470F4 23CS8415Anormally occupied by the P bit is used to indicate the location of the block start, SDOUT pin only, serial audiooutput port clock mus

24 DS470F4CS8415A8.6 Interrupt 2 Status (08h) (Read Only)For all bits in this register, a “1” means the associated interrupt condition has occurred at

DS470F4 25CS8415A8.10 Interrupt 2 Mode MSB (0Dh) and Interrupt 2 Mode LSB (0Eh)The two Interrupt Mode registers form a 2-bit code for each Interrupt R

26 DS470F4CS8415AORIG - SCMS generation indicator, decoded from the category code and the L bit.0 - Received data is 1st generation or higher1 - Recei

DS470F4 27CS8415A8.13 Receiver Error Mask (11h)The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If

28 DS470F4CS8415A8.15 User Data Buffer Control (13h)DETUI - D to E U-data buffer transfer inhibit bit.Default = ‘0’0 - Allow U-data D to E buffer tran

DS470F4 29CS8415A8.19 CS8415A I.D. and Version Register (7Fh) (Read Only)ID3:0 - ID code for the CS8415A. Permanently set to 0100VER3:0 - CS8415A revi

DS470F4 3CS8415ATABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ...

30 DS470F4CS8415A9. PIN DESCRIPTION - SOFTWARE MODEPin Name # Pin DescriptionSDA/CDOUT1Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) -

DS470F4 31CS8415AAGND7Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-nected to a common ground area

32 DS470F4CS8415A10.HARDWARE MODE The CS8415A has a hardware mode which allows using the device without a microcontroller. Hardware mode is selected b

DS470F4 33CS8415A11.PIN DESCRIPTION - HARDWARE MODEPin Name # Pin DescriptionCOPY1COPY Channel Status Bit (Output) - Reflects the state of the Copyrig

34 DS470F4CS8415ARMCK10Recovered Master Clock (Output) - Recovered master clock output when PLL is locked to the incoming AES3 stream. Frequency is 25

DS470F4 35CS8415A12. APPLICATIONS12.1 Reset, Power Down and Start-Up When RST is low, the CS8415A enters a low-power mode and all internal states are

36 DS470F4CS8415A13.APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS 13.1 AES3 Receiver External ComponentsThe CS8415A AES3 receiver is de

DS470F4 37CS8415A13.2 Isolating Transformer RequirementsPlease refer to the application note AN134: AES and SPDIF Recommended Transformers for resourc

38 DS470F4CS8415A14.APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT14.1 AES3 Channel Status (C) Bit ManagementThe CS8415A contains sufficie

DS470F4 39CS8415AA flowchart for reading the E buffer is shown in Figure 17. Since a D-to-E interrupt just occurred after read-ing, there is a substan

4 DS470F4CS8415A13. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS ... 3513.1 AES3 Receiver External Components

40 DS470F4CS8415AOne-byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes worthof information in 1 byte&a

DS470F4 41CS8415A15.APPENDIX C: PLL FILTER15.1 GeneralAn on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. F

42 DS470F4CS8415A15.2 External Filter Components15.2.1 GeneralThe PLL behavior is affected by the external filter component values. Figure 5 on page 1

DS470F4 43CS8415A15.3 Component Value SelectionWhen transitioning from one revision of the part another, component values may need to be changed. Whi

44 DS470F4CS8415A15.3.3 Jitter ToleranceShown in Figure 20 is the Receiver Jitter Tolerance template as illustrated in the AES3 and IEC60958-4specific

DS470F4 45CS8415A15.3.4 Jitter AttenuationShown in Figure 21, Figure 22, Figure 23, and Figure 24 are jitter attenuation plots for the various revi-si

46 DS470F4CS8415A16.REVISION HISTORY Release Date ChangesPP1 November 1999 1st Preliminary ReleasePP2 November 2000 2nd Preliminary ReleasePP3 May 20

DS470F4 5CS8415ALIST OF FIGURESFigure 1. Audio Port Master Mode Timing ...

6 DS470F4CS8415A1. CHARACTERISTICS AND SPECIFICATIONSAll Min/Max characteristics and specifications are guaranteed over the Specified Operating Condit

DS470F4 7CS8415ADIGITAL INPUT CHARACTERISTICSDIGITAL INTERFACE SPECIFICATIONS AGND = DGND = 0 V; all voltages with respect to 0 V. 5. At 5.0 V mode, V

8 DS470F4CS8415ASWITCHING CHARACTERISTICS - SERIAL AUDIO PORTSInputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.7. The active edges of OSCLK are progra

DS470F4 9CS8415ASWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODEInputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.12. If Fs is lower than 46.875 kHz