Cirrus-logic CDB42448 Manual do Utilizador descarregar pdf (Página 23)

CDB42448

DS648DB2 23

routes the FPGA data to the DSP. Refer to schematic Figure 14 on page 36.

5.6.3 ADC TO AUX SDIN (CS5341->AUX

)

Default = 0

0 - Enable

1 - Disable

Function:

This bit toggles a control line for the external data buffer to route the external ADC Data directly to the

AUX_SDIN port. When disabled, the FPGA will route the CS8416 SDOUT to the AUX_SDIN port.

5.6.4 DAC CLOCKS TO DSP (DAC->DSP

)

Default = 1

0 - Enable

1 - Disable

Function:

This bit toggles a control line for the external clock buffer to route the DAC sub clocks directly to the

DSP port (see Figure 7 on page 14).

5.6.5 ADC CLOCKS TO DSP (ADC->DSP

)

Default = 1

0 - Enable

1 - Disable

Function:

This bit toggles a control line for the external clock buffer to route the ADC sub clocks directly to the

DSP port (see Figure 7 on page 14).

5.6.6 DSP CLOCKS TO DAC (DSP->DAC

)

Default = 1

0 - Enable

1 - Disable

Function:

This bit toggles a control line for the external clock buffer to route the DSP clocks directly to the DAC

serial port (see Figure 7 on page 14).

5.6.7 DSP CLOCKS TO ADC (DSP->ADC

)

Default = 1

0 - Enable

1 - Disable

Function:

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