Cirrus-logic CDB42448 Manual do Utilizador

Copyright © Cirrus Logic, Inc. 2004(All Rights Reserved)Cirrus Logic, Inc.www.cirrus.comCDB42448Evaluation Board For CS42448Featuresz Single-ended/Sin

CDB4244810 DS648DB23.2. Internal Sub-Clock RoutingThe graphical description below shows the internal clock routing topology between the CS42448,CS8416

CDB42448DS648DB2 113.3. Internal Data RoutingThe graphical description below shows the internal data routing topology between the CS42448,CS8416, CS84

CDB4244812 DS648DB23.4. Internal TDM Conversion, MUXing and Control (TDMer)The graphical description below shows the routing topology of the TDM conve

CDB42448DS648DB2 133.5 External MCLK ControlSeveral sources for MCLK exist on the CDB42448. The crystal oscillator, Y1, will master theMCLK bus when n

CDB4244814 DS648DB23.6 Bypass Control - AdvancedThe DSP clocks and data may be routed through buffers directly to the CS42448, bypassingthe FPGA. This

CDB42448DS648DB2 154. FPGA REGISTER QUICK REFERENCEFunction 7 6 5 4 3 2 1 001hTDM Conver-sionDSP/CS8416 OUT1/OUT2 OUT1/OUT3 OUT1/OUT4 Reserved Reserve

CDB4244816 DS648DB25. FPGA REGISTER DESCRIPTIONAll registers are read/write. See the following bit definition tables for bit assignment information. T

CDB42448DS648DB2 175.2 CODEC SDINX CONTROL (ADDRESS 02H)5.2.1 SDIN4 MUX(SDIN4.MUX)Default = 11 Function:This MUX selects the data lines from the CS84

CDB4244818 DS648DB25.2.4 SDIN1 MUX(SDINX.MUX)Default = 10 Function:This MUX selects the data lines from the CS8416, DSP Header, the ADC and the TDM S

CDB42448DS648DB2 195.3.3 ADC MUX (ADC.CLK_MUX)Default = 11 Function:This MUX selects the sub-clock lines from the CS8416, DAC, DSP Header and the sub

CDB424482 DS648DB2TABLE OF CONTENTS1. SYSTEM OVERVIEW ...

CDB4244820 DS648DB2Function:This MUX selects the data lines from the ADC’s and the external ADC. The first 4 selections shown in Table 7 comes directl

CDB42448DS648DB2 215.5 CS8416 CONTROL (ADDRESS 05H)5.5.1 AUX OR DAC CLOCK SELECTION (AUX/DAC)Default = 10 - DAC Sub-Clocks to CS84161 - AUX Sub-Clocks

CDB4244822 DS648DB25.5.5 LEFT-JUSTIFIED OR I²S INTERFACE FORMAT (I²S/LJ)Default = 00 - Left-Justified1 - I²SFunction:Selects either I²S or Left Justif

CDB42448DS648DB2 23routes the FPGA data to the DSP. Refer to schematic Figure 14 on page 36. 5.6.3 ADC TO AUX SDIN (CS5341->AUX)Default = 00 - Enab

CDB4244824 DS648DB2This bit toggles a control line for the external clock buffer to route the DSP clocks directly to the ADC serial port (see Figure 7

CDB42448DS648DB2 25page 10). 5.7.4 DSP MCLK (MCLK_M/S)Default = 00 - DSP MCLK is a slave to the MCLK bus.1 - DSP MCLK masters MCLK bus.Function

CDB4244826 DS648DB25.8 CS5341 AND MISCELLANEOUS CONTROL (ADDRESS 08H)5.8.1 INT MCLK DIVIDE (1.5/2.0 DIVIDE)Default = 00 - Disabled1 - EnabledFunction:

CDB42448DS648DB2 27Function:Selects either I²S or Left Justified interface format for the CS5341. Reset to the CS5341 is toggled. 5.8.6 RESET (‘41_RST

CDB4244828 DS648DB26. CDB CONNECTORS AND JUMPERS CONNECTORReference Designator INPUT/OUTPUT SIGNAL PRESENT+5V J2 Input+5.0 V Power Supply+12V J5

CDB42448DS648DB2 29 JUMPER PURPOSE POSITION FUNCTION SELECTEDJ1 Selects source of voltage for the VA supply +3.3V*+5VVoltage source is +3.3 V regulato

CDB42448DS648DB2 3LIST OF FIGURESFigure 1. Advanced Register Tab - CS42448 ...

CDB4244830 DS648DB27. CDB BLOCK DIAGRAM CS42448CS8416S/PDIFInputy Differential toSingle-EndedOutputy Passive Filter oneach Legy Single-Ended

CDB42448DS648DB2 318. CDB SCHEMATICS Figure 9. CS42448

CDB4244832 DS648DB2 Figure 10. FPGA

CDB42448DS648DB2 33 Figure 11. S/PDIF Input & Output

CDB4244834 DS648DB2 Figure 12. Control Port

CDB42448DS648DB2 35 Figure 13. Buffers - FPGA Bypass

CDB4244836 DS648DB2 Figure 14. Buffers - DSP Routing

CDB42448DS648DB2 37 Figure 15. Analog Inputs

CDB4244838 DS648DB2 Figure 16. Auxiliary Input

CDB42448DS648DB2 39 Figure 17. Analog Outputs

CDB424484 DS648DB21. SYSTEM OVERVIEW The CDB42448 evaluation board is an excellent means for evaluating the CS42448 CODEC. An-alog and digital audio s

CDB4244840 DS648DB2 Figure 18. Power

CDB42448DS648DB2 419. CDB LAYOUT Figure 19. Silk Screen

CDB4244842 DS648DB2 Figure 20. Topside Layer

CDB42448DS648DB2 43 Figure 21. Bottom side Layer

CDB4244844 DS648DB210.REVISION HISTORY Revision Date ChangesDB1 July 2004 Initial ReleaseDB2 OCT 2004 Removed Bill of MaterialsLayer Changes: Correct

CDB42448DS648DB2 5clock on the OMCK input pin, and can operate in either the Left-Justified or I²S interface for-mat. Selections are made in the contr

CDB424486 DS648DB2Selections are made in the control port of the FPGA, accessible through the “FPGA” tab ofthe Cirrus Logic FlexGUI software. Refer to

CDB42448DS648DB2 72. SOFTWARE MODEThe CDB42448 is shipped with a Microsoft Windows® based GUI, which allows control over theCS42448 and FPGA registers

CDB424488 DS648DB2Figure 2. Advanced Register Tab - FPGA

CDB42448DS648DB2 93. FPGA SYSTEM OVERVIEWThe FPGA (U14) controls all digital signal routing between the CS42448, CS8406 CS8416,CS5341 and the DSP I/O