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CDB42448

DS648DB2 19

5.3.3 ADC MUX (ADC.CLK_MUX)

Default = 11

Function:

This MUX selects the sub-clock lines from the CS8416, DAC, DSP Header and the sub-clocks from

the TDMer internal to the FPGA (see Figure 3 on page 10).

5.3.4 FPGA CLOCKS TO ADC CLOCKS (FPGA->

ADC)

Default = 0

0 - FPGA Masters ADC clock bus

1 - FPGA Slave to ADC clock bus

Function:

This bit toggles a control line for the internal clock buffer to the ADC serial port (see Figure 3 on page

10).

5.4 CS8406 CONTROL (ADDRESS 04H)

5.4.1 RESET (RST)

Default = 1

0 - CS8406 held in reset

1 - CS8406 taken out of reset

Function:

This bit is used to reset the CS8406 and is held low for 300 µs upon FPGA initialization.

5.4.2 DATA MUX(MUX)

Default = 100

ADC.CLK_

MUX[1:0]

Clock Selection

CS8416

DAC

DSP ADC

TDMer

Table 6. Clocks to ADC

76543210

Reserved RST MUX2 MUX1 MUX0 128/256 Fs I²S/LJ T2P/ADC

MUX[2:0] Data Selection

000

ADC_SDOUT

001

ADC_SDOUT2

010

ADC_SDOUT3

011

ADC_SDOUT1

Table 7. Data to CS8406

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 43 44

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