Cirrus-logic EP7311 Manual do Utilizador descarregar pdf (Página 28)

28 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS506F2

EP7311

High-Performance, Low-Power System on Chip

LCD Interface

Parameter Symbol Min Max Unit

CL[2] falling to CL[1] rising delay time

t

CL1d

 10 25 ns

CL[1] falling to CL[2] rising delay time

t

CL2d

80 3,475 ns

CL[1] falling to FRM transition time

t

FRMd

300 10,425 ns

CL[1] falling to M transition time

t

Md

 10 20 ns

CL[2] rising to DD (display data) transition time

t

DDd

 10 20 ns

CL[2]

CL[1]

FRM

M

DD [3:0]

t

CL1d

t

FRMd

t

Md

t

DDd

t

CL2d

Figure 13. LCD Controller Timing Measurement

1 2 ... 23 24 25 26 27 28 29 30 31 32 33 ... 41 42

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