Cirrus-logic EP7311 Manual do Utilizador descarregar pdf (Página 19)

DS506F2 Copyright Cirrus Logic, Inc. 2011

EP7311

High-Performance, Low-Power System on Chip

SDRAM Burst Write Cycle

Note: 1. Timings are shown with CAS latency = 2

2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.

Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal

SDCLK

SDCS

SDRAS

SDCAS

SDQM

ADDR

DATA

SDMWE

ADRAS

ADCAS

D4D3D2

CSa

RAa

CAa

CSa

CSd

RAd

CSd

CAd

ADv

DAd

ADv

DAd

MWa

MWd

Figure 5. SDRAM Burst Write Cycle Timing Measurement

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 41 42

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Cirrus-logic EP7311 Manual do Utilizador Página 19