Cirrus-logic EP7309 Manual do Utilizador descarregar pdf (Página 22)

22 Copyright Cirrus Logic, Inc. 2011

EP7309

High-Performance, Low-Power System on Chip

LCD Interface

Parameter Symbol Min Max Unit

CL[2] falling to CL[1] rising delay time

CL1d

 10 25 ns

CL[1] falling to CL[2] rising delay time

CL2d

80 3,475 ns

CL[1] falling to FRM transition time

FRMd

300 10,425 ns

CL[1] falling to M transition time

 10 20 ns

CL[2] rising to DD (display data) transition time

DDd

 10 20 ns

CL[2]

CL[1]

FRM

DD [3:0]

CL1d

FRMd

DDd

CL2d

Figure 9. LCD Controller Timing Measurement

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 41 42

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