Cirrus-logic CS5372A Manual do Utilizador descarregar pdf (Página 26)

CS5371A CS5372A

26 DS748F3

VREF+

Positive Voltage Reference Input, pin 5

Input for an external +2.500 V voltage reference relative to VREF-.

VREF-

Negative Voltage Reference Input, pin 6

This pin should be tied to VA- near the voltage reference output.

Digital Inputs

MCLK

Modulator Clock Input, pin 19

A CMOS compatible clock input for the modulator internal master clock, nominally 2.048 MHz

with an amplitude equal to the VD digital power supply.

MSYNC

Modulator Sync Input, pin 20

A low to high transition resets the internal clock phasing of the modulator. This assures the

sampling instant and modulator data output are synchronous to the external system.

OFST

Offset Mode Select, pin 14

When high, adds approximately -60 mV or -35 mV of internal differential offset to the analog

input signal to guarantee any ΔΣ idle tones are removed. When low, no offset is added.

PWDN

Power-down Mode, pin 24

When high, the modulator is in power-down mode. Halting MCLK while in power down mode

reduces modulator power dissipation further.

Digital Outputs

MDATA

Modulator Data Output, pin 21

Modulator data is output as a 1-bit serial data stream at 512 kHz with an MCLK input of

2.048 MHz.

MFLAG

Modulator Flag Output, pin 22

A high level output indicates the modulator is unstable due to an over-range on the analog

inputs.

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Cirrus-logic CS5372A Manual do Utilizador Página 26