Cirrus-logic CS42426 Manual do Utilizador descarregar pdf (Página 47)

DS604F2 47

CS42426

6.6.4 INTERPOLATION FILTER SELECT (FILT_SEL)

Default = 0

Function:

This feature allows the user to select whether the DAC interpolation filter has a fast- or slow roll-off.

For filter characteristics, please See “D/A Digital Filter Characteristics” on page 10.

0 - Fast roll-off.

1 - Slow roll-off.

6.6.5 HIGH-PASS FILTER FREEZE (HPF_FREEZE)

Default = 0

Function:

When this bit is set, the internal high-pass filter for the selected channel will be disabled. The current

DC offset value will be frozen and continue to be subtracted from the conversion result. See “A/D Dig-

ital Filter Characteristics” on page 8.

6.6.6 DAC SERIAL PORT MASTER/SLAVE SELECT (DAC_SP M/S

)

Default = 0

Function:

In Master Mode, DAC_SCLK and DAC_LRCK are outputs. Internal dividers will divide the master

clock to generate the serial clock and left/right clock. In Slave Mode, DAC_SCLK and DAC_LRCK

become inputs.

If the DAC_SP is in Slave Mode, DAC_LRCK must be present for proper device operation.

6.6.7 ADC SERIAL PORT MASTER/SLAVE SELECT (ADC_SP M/S

)

Default = 0

Function:

In Master Mode, ADC_SCLK and ADC_LRCK are outputs. Internal dividers will divide the master

clock to generate the serial clock and left/right clock. In Slave Mode, ADC_SCLK and ADC_LRCK

become inputs.

If the ADC_SP is in Slave Mode, ADC_LRCK must be present for proper device operation.

To use the PLL to lock to ADC_LRCK, the ADC_SP must be in Slave Mode. When using the PLL to

lock to LRCK, if ADC_SDOUT is configured to be clocked by the ADC_SP, both ADC_SCLK and AD-

C_LRCK must be present. If ADC_SDOUT is configured to be clocked by the DAC_SP, only the AD-

C_LRCK signal must be applied.

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Cirrus-logic CS42426 Manual do Utilizador Página 47