Cirrus-logic CS4360 Manual do Utilizador descarregar pdf (Página 18)

CS4360

18 DS517F2

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Continued)

Notes: 10. t

spi

only needed before first falling edge of CS after RST rising edge. t

spi

= 0 at all other times.

11. Data must be held for sufficient time to bridge the transition time of CCLK.

12. For f

sclk

< 1 MHz.

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency f

sclk

-6MHz

RST

Rising Edge to CS Falling

srs

500 - ns

CCLK Edge to CS

Falling (Note 10)

spi

500 - ns

High Time Between Transmissions

csh

1.0 - µs

Falling to CCLK Edge

css

20 - ns

CCLK Low Time t

scl

-ns

CCLK High Time t

sch

-ns

CDIN to CCLK Rising Setup Time t

dsu

40 - ns

CCLK Rising to DATA Hold Time

(Note 11) t

15 - ns

Rise Time of CCLK and CDIN

(Note 12) t

- 100 ns

Fall Time of CCLK and CDIN

(Note 12) t

- 100 ns

MCLK

-----------------

MCLK

-----------------

dsu

sch

scl

CCLK

CDIN

css

csh

spi

srs

RST

Figure 14. Control Port Timing - SPI Mode

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 36 37

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