Cirrus-logic CS42L51 Manual do Utilizador descarregar pdf (Página 78)

78 DS679F1

CS42L51

7.3 ADC_FILT+ Capacitor Effects on THD+N

The value of the capacitor on the ADC_FILT+ pin, 16, affects the low frequency total harmonic distortion +

noise (THD+N) performance of the ADC. Larger capacitor values yield significant improvement in THD+N

at low frequencies. Figure 33 shows the THD+N versus frequency for the ADC analog input. Plots were tak-

en from the CDB42L51 using an Audio Precision analyzer.

-100

-96

-92

-88

-84

-80

-76

-72

-68

-64

20 20k50 100 200 500 1k 2k 5k 10k

Figure 33. ADC THD+N vs. Frequency w/Capacitor Effects

1 µF

Legend –

Capacitor Value on ADC_FILT+

10 µF

22 µF

1 2 ... 73 74 75 76 77 78 79 80 81 82 83 ... 87 88

DIGITAL to ANALOG FEATURES 1
ANALOG to DIGITAL FEATURES 1
SYSTEM FEATURES 2
™ Control) 2
GENERAL DESCRIPTION 2
TABLE OF CONTENTS 3
LIST OF FIGURES 5
LIST OF TABLES 6
DS679F1 7 7
7
Pin Name # Pin Description 7
8 DS679F1 8
10 DS679F1 10
DS679F1 11 11
ABSOLUTE MAXIMUM RATINGS 12
SDOUT Code with HPF On 13
DS679F1 15 15
VA = 1.8V 16
16 DS679F1 16
VA = 2.5V (nominal) 16
DS679F1 17 17
18 DS679F1 18
DS679F1 19 19
20 DS679F1 20
DS679F1 21 21
CONTROL PORT 22
24 DS679F1 24
Parameters Min Typ Max Units 24
POWER CONSUMPTION 25
4. APPLICATIONS 26
4.2 Hardware Mode 27
4.3 Analog Inputs 28
DS679F1 29 29
2π 50 kΩ()1 µF() 30
4.3.6 MIC & PGA Gain 31
32 DS679F1 32
2.) The ALC maintains 32
4.3.8 Noise Gate 33
4.4 Analog Outputs 34
4.4.1 De-Emphasis Filter 34
4.4.2 Volume Controls 35
4.4.3 Mono Channel Mixer 35
4.4.4 Beep Generator 35
4.4.5 Tone Control 36
4.4.6 Limiter 36
DS679F1 37 37
4.4.8 On-Chip Charge Pump 38
4.5 Serial Port Clocking 38
4.5.1 Slave 39
4.5.2 Master 39
4.6 Digital Interface Formats 40
4.7 Initialization 41
42 DS679F1 42
4.10 Software Mode 43
4.10.1 SPI Control 43
4.10.2 I²C Control 43
44 DS679F1 44
4.10.3.1 Map Increment (INCR) 45
5. REGISTER QUICK REFERENCE 46
DS679F1 47 47
48 DS679F1 48
6. REGISTER DESCRIPTION 49
50 DS679F1 50
Power Down PGA X (PDN_PGAX) 50
Power Down ADC X (PDN_ADCX) 50
Power Down (PDN) 50
Auto-Detect Speed Mode (AUTO) 50
52 DS679F1 52
Master/Slave Mode (M/S) 52
6.5 MIC Control (Address 05h) 53
6.6 ADC Control (Address 06h) 54
56 DS679F1 56
ADCX Channel Mute (ADCX_MUTE) 56
6.9 DAC Control (Address 09h) 58
6.18 AOUTx Volume Control: 66
74 DS679F1 74
N CHRG_FREQ[3:0] Frequency 74
7. ANALOG PERFORMANCE PLOTS 75
76 DS679F1 76
NOTE: Graph shows the out 76
DS679F1 77 77
VA_HP = VA = 1.8 V 77
78 DS679F1 78
8.1 Auto Detect Enabled 79
8.2 Auto Detect Disabled 80
9. PCB LAYOUT CONSIDERATIONS 81
82 DS679F1 82
11.PARAMETER DEFINITIONS 83
12.PACKAGE DIMENSIONS 84
THERMAL CHARACTERISTICS 84
13.ORDERING INFORMATION 85
14.REFERENCES 85
15.REVISION HISTORY 86
DS679F1 87 87
Revision Changes 87
88 DS679F1 88

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