Cirrus-logic CS42L55 Manual do Utilizador

Copyright © Cirrus Logic, Inc. 2007(All Rights Reserved)http://www.cirrus.comNOVEMBER '07DS773F1Ultra Low Power, Stereo CODEC w/Class H Headphone

10 DS773F1CS42L552. TYPICAL CONNECTION DIAGRAM Note 22.2 µFNote 1Analog Input 1Analog Input 21 µFGND/Thermal PadVL0.1 µF+1.65 V to +3.47 VSCLSDARESET2

DS773F1 11CS42L553. CHARACTERISTIC AND SPECIFICATION TABLES RECOMMENDED OPERATING CONDITIONSGND = AGND = 0 V, all voltages with respect to ground.

12 DS773F1CS42L55ANALOG INPUT CHARACTERISTICSTest Conditions (unless otherwise specified): Connections to the CS42L55 are shown in the Figure 1. &quo

DS773F1 13CS42L55ADC DIGITAL FILTER CHARACTERISTICS Notes:8. Response is clock-dependent and will scale with Fs. Note that the response plots (Figur

14 DS773F1CS42L55HP OUTPUT CHARACTERISTICSTest conditions (unless otherwise specified): Connections to the CS42L55 are shown in the “Typical Connectio

DS773F1 15CS42L55LINE OUTPUT CHARACTERISTICSTest conditions (unless otherwise specified): Connections to the CS42L55 are shown in the “Typical Connect

16 DS773F1CS42L55ANALOG PASSTHROUGH CHARACTERISTICSTest Conditions (unless otherwise specified): Connections to the CS42L55 are shown in the “Typical

DS773F1 17CS42L55SWITCHING SPECIFICATIONS - SERIAL PORTInputs: Logic 0 = GND = AGND, Logic 1 = VL, LRCK, SCLK, SDOUT CLOAD = 15 pF. Notes: 17. After p

18 DS773F1CS42L55SWITCHING SPECIFICATIONS - CONTROL PORTInputs: Logic 0 = GND = AGND, Logic 1 = VL, SDA CL=30pF.Notes:19. Data must be held for suffic

DS773F1 19CS42L55POWER SUPPLY REJECTION (PSRR) CHARACTERISTICS Test Conditions (unless otherwise specified): Connections to the CS42L55 are shown in t

2 DS773F1CS42L55SYSTEM FEATURES High Performance 24-bit Converters – Multi-bit Delta Sigma Architecture Integrated High Efficient Power Management R

20 DS773F1CS42L55POWER CONSUMPTION - ALL SUPPLIES = 1.8 V Operation Test Condi-tions (unless otherwise specified): All zeros input, slave mode, sample

DS773F1 21CS42L55POWER CONSUMPTION - ALL SUPPLIES = 2.5 V Notes:23. When “Off”, RESET pin and clock/data lines held LO; when in “standby”, lines are h

22 DS773F1CS42L554. APPLICATIONS4.1 Overview4.1.1 Basic ArchitectureThe CS42L55 is a highly integrated, ultra-low power, 24-bit audio CODEC comprised

DS773F1 23CS42L554.2 Analog Inputs Referenced Control Register LocationAnalog Front EndPGAxMUXPDN_ADCxPGAxVOL[5:0]PGAB=AANLGZCxADCxMUX[1:0]INV_ADCxPDN

24 DS773F1CS42L554.2.1 Pseudo-Differential InputsThe CS42L55 implements a pseudo-differential input stage. The AINxREF inputs are intended to be useda

DS773F1 25CS42L554.3 Analog In to Analog Out PassthroughThe CS42L55 accommodates analog routing of the analog input signal directly to the headphone a

26 DS773F1CS42L554.4 Analog Outputs Referenced Control Register LocationDSPPDN_DSPDEEMPHPMIXxMUTEPMIXxVOL[6:0]INV_PCMxPCMxSWAP[1:0]AMIXxMUTEAMIXxVOL[6

DS773F1 27CS42L554.5 Class H AmplifierThe CS42L55 headphone and line output amplifiers use a patented Cirrus Logic Bi-Modal Class H technol-ogy. This

28 DS773F1CS42L554.5.1.1 Standard Class AB Operation (Mode 01 and 10)When the Adaptive Power bits are set to either 01 or 10, the rail voltages suppli

DS773F1 29CS42L554.5.1.3 Adapted to Output Signal (Mode 11)When the Adaptive Power bits are set to 11, the CS42L55 decides which of the two sets of ra

DS773F1 3CS42L55TABLE OF CONTENTS1. PIN DESCRIPTIONS ...

30 DS773F1CS42L55When the charge pump transitions from the higher set of rail voltages to the lower set, there is a one sec-ond delay before the charg

DS773F1 31CS42L554.5.3 EfficiencyAs discussed in previous sections, the amplifiers internal to the CS42L55 operate from one of two sets ofrail voltage

32 DS773F1CS42L55 4.7 LimiterWhen enabled, the limiter monitors the digital input signal before the DAC modulators, detects when levelsexceed the maxi

DS773F1 33CS42L55MAX[2:0]Output(after Limiter)InputRRATE[5:0]ARATE[5:0]VolumeLimiterCUSH[2:0] ATTACK/RELEASE SOUND CUSHIONMAX[2:0]Figure 19. Peak Det

34 DS773F1CS42L554.8 Serial Port ClockingThe CODEC serial audio interface port operates either as a slave or master. It accepts externally generatedcl

DS773F1 35CS42L55After the PDN bit is released and MCLK is valid, the quiescent voltage, VQ, and the internal voltage refer-ence, FILT+, will begin po

36 DS773F1CS42L554.11.1 Recommended Power-Down Sequence1. To minimize pops on the headphone or line amplifier, each respective analog volume control m

DS773F1 37CS42L55signal. The zero cross timeout, however, is dependent on the serial port clock domain. Thus, to fully power down, the ADC must briefl

38 DS773F1CS42L554.14 Control Port OperationThe control port is used to access the registers allowing the CODEC to be configured for the desired oper-

DS773F1 39CS42L55Receive acknowledge bit.Send stop condition, aborting write. Send start condition. Send 10010101 (chip address & read operation).

4 DS773F1CS42L555. REGISTER QUICK REFERENCE ... 4

40 DS773F1CS42L555. REGISTER QUICK REFERENCE(Default values are shown below the bit names) I²C Address: 1001010[R/W] - 10010100 = 0x94(Write); 1001010

DS773F1 41CS42L551BhHeadphone B VolumeHPBMUTE HPBVOL6 HPBVOL5 HPBVOL4 HPBVOL3 HPBVOL2 HPBVOL1 HPBVOL0p57 0 0 0 0 000 01ChLine AVolumeLINEAMUTE LINEAVO

42 DS773F1CS42L556. REGISTER DESCRIPTION Except for the chip I.D., revision register, and status register, which are Read Only, all registers are Read

DS773F1 43CS42L556.3 Power Control 2 (Address 03h)6.3.1 Headphone Power ControlConfigures how the HPDETECT pin, 29, controls the power for the headpho

44 DS773F1CS42L556.4.3 SCLK Equals MCLKConfigures the SCLK signal source and speed for master mode.6.4.4 MCLK Divide By 2Configures a divide of the in

DS773F1 45CS42L556.5.2 32 kHz Sample Rate GroupSpecifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz.6.5.3 Internal MCLK/LR

46 DS773F1CS42L556.7.2 Analog Zero CrossConfigures when the signal level changes occur for the analog volume controls. Note: If the signal does not en

DS773F1 47CS42L556.8.2 Line Input SelectSelects the specified analog input signal into line amplifier x. Note: The PGA path must not be selected while

48 DS773F1CS42L556.10 Misc. ADC Control (Address 0Ah)6.10.1 ADC Channel B=AConfigures independent or ganged volume control of the ADC and the ALC. 6.

DS773F1 49CS42L556.11 PGA x MUX, Volume:PGA A (Address 0Bh) & PGA B (Address 0Ch)6.11.1 BoostxConfigures a +20 dB boost on channel x. 6.11.2 PGA x

DS773F1 5CS42L556.13.4 Invert PCM Signal Polarity ...

50 DS773F1CS42L556.12 ADCx Attenuator Control: ADCAATT (Address 0Dh) & ADCBATT (Address 0Eh)6.12.1 ADCx VolumeSets the volume of the ADC signal.

DS773F1 51CS42L556.13.4 Invert PCM Signal PolarityConfigures the polarity of the digital input signal. 6.13.5 Master Playback MuteConfigures a digital

52 DS773F1CS42L556.15 PCMx Mixer Volume:PCMA (Address 12h) & PCMB (Address 13h)6.15.1 PCM Mixer Channel x MuteConfigures a digital mute on the PCM

DS773F1 53CS42L556.16 Beep Frequency & On Time (Address 14h)6.16.1 Beep Frequency Sets the frequency of the beep signal. Notes:1. This setting mus

54 DS773F1CS42L556.16.2 Beep On TimeSets the on duration of the beep signal. Notes:1. This setting must not change when BEEP is enabled.2. Beep on tim

DS773F1 55CS42L556.17.2 Beep Volume Sets the volume of the beep signal.Note: This setting must not change when BEEP is enabled.6.18 Beep & Tone Co

56 DS773F1CS42L556.18.3 Bass Corner Frequency Sets the corner frequency for the bass shelving filter.6.18.4 Tone Control Enable Configures the treble

DS773F1 57CS42L556.20 Master Volume Control:MSTA (Address 18h) & MSTB (Address 19h)6.20.1 Master Volume Control Sets the volume of the signal out

58 DS773F1CS42L556.22 Line Volume Control:LINEA (Address 1Ch) & LINEB (Address 1Dh)6.22.1 Line Channel x MuteConfigures an analog mute on the line

DS773F1 59CS42L556.23 Analog Input Advisory Volume (Address 1Eh)6.23.1 Analog Input Advisory Volume Defines the maximum analog input volume level used

6 DS773F1CS42L556.30 ALC Release Rate (Address 25h) ... 6

60 DS773F1CS42L556.25 ADC & PCM Channel Mixer (Address 20h)6.25.1 PCM Mix Channel Swap Configures a mix/swap of the PCM Mix to the headphone/line

DS773F1 61CS42L556.26.2 Limiter Cushion Threshold Sets the minimum level at which to disengage the Limiter’s attenuation at the release rate (LIMRRATE

62 DS773F1CS42L556.27.3 Limiter Release Rate Sets the rate at which the limiter releases the digital attenuation from levels below the CUSH[2:0] thres

DS773F1 63CS42L556.29.2 ALC Attack RateSets the rate at which the ALC applies analog and/or digital attenuation from levels above the AMAX[2:0]thresho

64 DS773F1CS42L556.31 ALC Threshold (Address 26h)6.31.1 ALC Maximum ThresholdSets the maximum level, below full-scale, at which to limit and attenuate

DS773F1 65CS42L556.32.2 Noise Gate EnableConfigures the noise gate. 6.32.3 Noise Gate Threshold and BoostTHRESH sets the threshold level of the noise

66 DS773F1CS42L556.33.3 Limiter Soft Ramp DisableConfigures an override of the digital soft ramp setting. 6.34 Status (Address 29h) (Read Only)For bi

DS773F1 67CS42L556.34.5 ADCx Overflow (Read Only)Indicates the over-range status in the ADC signal path. 6.35 Charge Pump Frequency (Address 2Ah)6.35

68 DS773F1CS42L557. PCB LAYOUT CONSIDERATIONS7.1 Power SupplyAs with any high-resolution converter, the CS42L55 requires careful attention to power su

DS773F1 69CS42L558. ANALOG VOLUME NON-LINEARITY (DNL & INL)PGA Volume SettingActual Output Volume, dB-8-6-4-2024681012-6-5-4-3-2-10123456789101112

DS773F1 7CS42L55Figure 18.Beep Configuration Options ...

70 DS773F1CS42L559. ADC & DAC DIGITAL FILTERS 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.91−100−90−80−70−60−50−40−30−20−100Frequency (normalized to Fs)A

DS773F1 71CS42L5510.PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over th

72 DS773F1CS42L5511.PACKAGE DIMENSIONS (Unless otherwise specified, linear tolerance is ±0.05 mm, and angular tolerance is ±2 deg.) 1. Controlling dim

DS773F1 73CS42L5512.ORDERING INFORMATION13.REFERENCES1. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000. http://www.semico

8 DS773F1CS42L551. PIN DESCRIPTIONS Pin Name # Pin DescriptionSDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial

DS773F1 9CS42L551.1 I/O Pin CharacteristicsInput and output levels and associated power supply voltage are shown in the table below. Logic levelsshoul