Cirrus-logic CS4234 Manual do Utilizador Página 30

  • Descarregar
  • Adicionar aos meus manuais
  • Imprimir
  • Página
    / 79
  • Índice
  • MARCADORES
  • Avaliado. / 5. Com base em avaliações de clientes
Vista de página 29
DS899F1 30
CS4234
SDIN1
Input Data
1.1.A
[31:8]
Input Data
1.1.B
[7:0]
Input Data
1.2.A
[31:8]
Input Data
1.2.B
[7:0]
Input Data
1.3.A
[31:8]
Input Data
1.3.B
[7:0]
Input Data
1.4.A
[31:8]
x
[7:0]
Input Data
1.5.A
[31:8]
Input Data
1.5.B
[7:0]
Input Data
1.6.A
[31:8]
Input Data
1.6.B
[7:0]
Input Data
1.7.A
[31:8]
Input Data
1.7.B
[7:0]
Input Data
1.8.A
[31:8]
x[7:0]
SDIN2
Input Data
2.1
[31:8]
x
[7:0]
Input Data
2.2
[31:8]
x
[7:0]
Input Data
2.3
[31:8]
x[7:0]
Input Data
2.4
[31:8]
x
[7:0]
Input Data
2.5
[31:8]
x
[7:0]
Input Data
2.6
[31:8]
x[7:0]
Input Data
2.7
[31:8]
x[7:0]
Input Data
2.8
[31:8]
x[7:0]
SDOUT
ADC1
Data[31:8]
0's
[7:0]
ADC2 Data
[31:8]
0's
[7:0]
ADC3 Data
[31:8]
0's
[7:0]
ADC4
Data[31:8]
0's
[7:0]
SDOUT with
Sidechain
ADC1
Data[31:8]
0's
[7:0]
ADC2 Data
[31:8]
0's
[7:0]
ADC3 Data
[31:8]
0's
[7:0]
ADC4 Data
[31:8]
0's
[7:0]
FS = 48/96kHz
MCLK = 12.288/24.576MHz
Slot 1 [31:0] Slot 2 [31:0]
SCLK = 12.288/24.576MHz
Slot 3 [31:0] Slot 4 [31:0] Slot 5 [31:0] Slot 6 [31:0] Slot 7 [31:0] Slot 8 [31:0]
0's
[31:0]
0's
[31:0]
0's
[31:0]
0's
[31:0]
Output Data
(SDIN2 Slot 1)
Output Data
(SDIN2 Slot 2)
Output Data
(SDIN2 Slot 3)
Output Data
(SDIN2 Slot 4)
SDIN1
Input Data
1.1.A
[31:8]
Input Data
1.1.B
[7:0]
Input Data
1.4.A
[31:8]
x
[7:0]
Input Data
1.5.A
[31:8]
Input Data
1.5.B
[7:0]
Input Data
1.8.A
[31:8]
x
[7:0]
Input Data
1.9.A
[31:8]
Input Data
1.9.B
[7:0]
Input Data
1.12.A
[31:8]
x
[7:0]
Input Data
1.13.A
[31:8]
Input Data
1.13.B
[7:0]
Input Data
1.16.A
[31:8]
x
[7:0]
SDIN2
Input Data
2.1
[31:8]
x
[7:0]
Input Data
2.4
[31:8]
x
[7:0]
Input Data
2.5
[31:8]
x
[7:0]
Input Data
2.8
[31:8]
x
[7:0]
Input Data
2.9
[31:8]
x
[7:0]
Input Data
2.12
[31:8]
x
[7:0]
Input Data
2.13
[31:8]
x
[7:0]
Input Data
2.16
[31:8]
x
[7:0]
SDOUT
ADC1 Data
[31:8]
0's
[7:0]
ADC4 Data
[31:8]
0's
[7:0]
SDOUT with
Sidechain
ADC1 Data
[31:8]
0's
[7:0]
ADC4 Data
[31:8]
0's
[7:0]
MCLK = 24.576MHz
FS = 48kHz
SCLK = 24.576MHz
Slot 1 [31:0]
Slot 4 [31:0] Slot 5 [31:0]
0's
[31:0]
Output Data
(SDIN2 Slot 1)
Slot 8 [31:0] Slot 9 [31:0]
0's
[31:0]
0's
[31:0]
Output Data
(SDIN2 Slot 4)
Output Data
(SDIN2 Slot 5)
Slot 12 [31:0] Slot 13 [31:0]
Slot 16 [31:0]
0's
[31:0]
0's
[31:0]
0's
[31:0]
Output Data
(SDIN2 Slot 8)
Output Data
(SDIN2 Slot 9)
Output Data
(SDIN2 Slot 12)
Figure 16. Serial Data Coding and Extraction Options within the TDM Streams
Vista de página 29
1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 78 79

Comentários a estes Manuais

Sem comentários