Cirrus-logic AN131 Manual do Utilizador descarregar pdf (Página 4)

AN131

4 AN131REV2

3.5 Acquiring Conversions

To acquire a conversion the subroutine convert is

called. For single conversions on one physical

channel, the MC (multiple conversion) and the LP

(loop) bits in the configuration register must be log-

ic 0. To prevent corruption of the configuration

save the contents. This information is stored in the

variables HIGHBYTE, MIDBYTE and LOW-

BYTE. Then the MC, LP, and RC (read convert)

bits are masked to logic 0, and the new information

is written back to the ADC’s configuration register.

A conversion is initiated using Setup 1 by sending

the command 0x80 to the converter. At this time,

the controller polls MOSI (SDO) until it falls to a

logic 0 level (see Figure 5). After SDO falls, con-

vert calls send_spi to send one byte of all 0’s to the

converter to clear the SDO flag. The 68HC05 then

reads the conversion data word by calling

receive_spi three times. Figure 6 depicts how the

16 and 24-bit data words are stored in the memory

locations HIGHBYTE, MIDBYTE, and LOW-

BYTE.

4. MAXIMUM SCLK RATE

A machine cycle in the 68HC05 consists of 2 oscil-

lator periods or 500 ns if the microcontroller’s os-

cillator frequency is 4 MHz. Since the

CS5521/22/23/24/28’s maximum SCLK rate is

2 MHz, additional no operation (NOP) delays may

be necessary to reduce the transfer rate if the micro-

controller system requires higher rate oscillators.

Figure 3. Write-Cycle Timing

Figure 4. Read-Cycle Timing

1 2 3 4 5 6 7 8 9 ... 13 14

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