Cirrus-logic CS5534-AS Manual do Utilizador

Consulte online ou descarregue Manual do Utilizador para Hardware Cirrus-logic CS5534-AS. Cirrus Logic CS5534-AS User Manual Manual do Utilizador

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Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
http://www.cirrus.com
CS5531/32/33/34-AS
16-bit and 24-bit ADCs with Ultra-low-noise PGIA
Features
Chopper-stabilized PGIA (Programmable
Gain Instrumentation Amplifier, 1x to 64x)
12 nV/Hz @ 0.1 Hz (No 1/f noise) at 64x
1200 pA Input Current with Gains >1
Delta-sigma Analog-to-digital Converter
Linearity Error: 0.0007% FS
Noise Free Resolution: Up to 23 bits
Two- or Four-channel Differential MUX
Scalable Input Span via Calibration
±5 mV to differential ±2.5V
Scalable V
REF
Input: Up to Analog Supply
Simple Three-wire Serial Interface
SPI™ and Microwire™ Compatible
Schmitt Trigger on Serial Clock (SCLK)
R/W Calibration Registers Per Channel
Selectable Word Rates: 6.25 to 3,840 Sps
Selectable 50 or 60 Hz Rejection
Power Supply Configurations
VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
VA+ = +3 V; VA- = -3 V; VD+ = +3 V
General Description
The CS5531/32/33/34 are highly integrated ∆Σ Analog-
to-Digital Converters (ADCs) which use charge-balance
techniques to achieve 16-bit (CS5531/33) and 24-bit
(CS5532/34) performance. The ADCs are optimized for
measuring low-level unipolar or bipolar signals in weigh
scale, process control, scientific, and medical
applications.
To accommodate these applications, the ADCs
come as
either two-channel (CS5531/32) or four-channel
(CS5533/34) devices and include a very low noise chop-
per-stabilized instrumentation amplifier (6 nV/Hz
@ 0.1
Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and
64×. These ADCs also include a fourth order ∆Σ modu-
lator followed by a digital filter
which provides twenty
selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30,
50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600,
1920, 3200, and 3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a micro-
controller, the converters include a simple three-wire se-
rial interface which is SPI and Microwire compatible with
a Schmitt-trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options makes these ADCs ideal
solutions for weigh scale and process control
applications.
ORDERING INFORMATION
See page 47
VA+ C1 C2 VREF+ VREF- VD+
DIFFERENTIAL
4
TH
ORDER
∆Σ
MODULATOR
PGIA
1,2,4,8,16
PROGRAMMABLE
SINC FIR FILTER
MUX
(CS5533/34
SHOWN)
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
SERIAL
INTERFACE
LATCH
CLOCK
GENERATOR
CALIBRATION
SRAM/CONTROL
LOGIC
DGND
CS
SDI
SDO
SCLK
OSC2OSC1A1A0/GUARDVA-
32,64
OCT ‘08
DS289F5
Vista de página 0
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Resumo do Conteúdo

Página 1 - CS5531/32/33/34-AS

Copyright © Cirrus Logic, Inc. 2008(All Rights Reserved)http://www.cirrus.comCS5531/32/33/34-AS16-bit and 24-bit ADCs with Ultra-low-noise PGIAFeature

Página 2

CS5531/32/33/34-AS10 DS289F5SWITCHING CHARACTERISTICS (VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels:

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CS5531/32/33/34-ASDS289F5 11CSSCLKMSBMSB-1LSBSDIt3t6t4 t5 t1t2Figure 1. SDI Write Timing (Not to Scale)CSSCLKMSB MSB-1LSBSDOt7t9t8t1t2Figure 2. SDO

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CS5531/32/33/34-AS12 DS289F52. GENERAL DESCRIPTIONThe CS5531/32/33/34 are highly integrated ∆Σ An-alog-to-Digital Converters (ADCs) which usecharge-b

Página 5

CS5531/32/33/34-ASDS289F5 13instrumentation amplifier is typically 1200 pAover -40°C to +85°C (MCLK=4.9152 MHz).The common-mode plus signal range

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CS5531/32/33/34-AS14 DS289F52.1.4. No Offset DACAn offset DAC was not included in the CS553Xfamily because the high dynamic range of the con-verter e

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CS5531/32/33/34-ASDS289F5 15instruct the converter to perform single or multipleconversions or calibrations with the converter inthe mode defined by o

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CS5531/32/33/34-AS16 DS289F5caused an operational issue for customers because their start-up sequence includes writing a word (with RS=0) into the con

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CS5531/32/33/34-ASDS289F5 172.2.2. Command Register Quick Reference D7(MSB) D6 D5 D4 D3 D2 D1 D00 ARA CS1 CS0 R/WRSB2 RSB1 RSB0BIT NAME VALUE FUNCTIO

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CS5531/32/33/34-AS18 DS289F52.2.3. Command Register DescriptionsREAD/WRITE ALL OFFSET CALIBRATION REGISTERSFunction: These commands are used to acces

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CS5531/32/33/34-ASDS289F5 19READ/WRITE INDIVIDUAL GAIN REGISTERFunction: These commands are used to access each gain register separately. CS1 - CS0 de

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CS5531/32/33/34-AS2 DS289F5TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ...4ANALOG C

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CS5531/32/33/34-AS20 DS289F5PERFORM CONVERSIONFunction: These commands instruct the ADC to perform either a single, fully-settled conversion or con-ti

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CS5531/32/33/34-ASDS289F5 21PERFORM CALIBRATIONFunction: These commands instruct the ADC to perform a calibration on the physical input channel se-lec

Página 15

CS5531/32/33/34-AS22 DS289F52.2.4. Serial Port InterfaceThe CS5531/32/33/34’s serial interface consists offour control lines: CS, SDI, SDO, SCLK. Fig

Página 16

CS5531/32/33/34-ASDS289F5 232.2.5. Reading/Writing On-Chip RegistersThe CS5531/32/33/34’s offset, gain, configuration,and channel-setup registers are

Página 17

CS5531/32/33/34-AS24 DS289F5ter is read. The on-chip registers are initialized tothe following default states:After reset, the RS bit should be writte

Página 18

CS5531/32/33/34-ASDS289F5 25from VA+ and VA-. Their output voltage will belimited to the VA+ voltage for a logic 1 and VA-for a logic 0.2.3.7. Offset

Página 19

CS5531/32/33/34-AS26 DS289F52.3.9. Configuration Register Descriptions PSS (Power Save Select)[31]0 Standby Mode (Oscillator active, allows quick pow

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CS5531/32/33/34-ASDS289F5 27Filter Rate Select, FRS[19]0 Use the default output word rates.1 Scale all output word rates and their corresponding filte

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CS5531/32/33/34-AS28 DS289F52.4.1. Channel-Setup Register Descriptions CS1-CS0 (Channel Select Bits) [31:30] [15:14]00 Select physical channel 1 (All

Página 22

CS5531/32/33/34-ASDS289F5 29U/B (Unipolar / Bipolar) [22] [6]0 Select Bipolar mode.1 Select Unipolar mode.OL1-OL0 (Output Latch Bits) [21:20] [5:4]The

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CS5531/32/33/34-ASDS289F5 3LIST OF FIGURESFigure 1. SDI Write Timing (Not to Scale)...

Página 24

CS5531/32/33/34-AS30 DS289F52.5. CalibrationCalibration is used to set the zero and gain slope ofthe ADC’s transfer function. The CS5531/32/33/34offe

Página 25

CS5531/32/33/34-ASDS289F5 312.5.4. Performing CalibrationsTo perform a calibration, the user must send a com-mand byte with its MSB = 1, its pointer

Página 26

CS5531/32/33/34-AS32 DS289F52.5.6. System CalibrationFor the system calibration functions, the user mustsupply the converter’s calibration signals wh

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CS5531/32/33/34-ASDS289F5 33crocontroller and the ADC, and may prematurelyhalt the calibration cycle.For maximum accuracy, calibrations should be per-

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CS5531/32/33/34-AS34 DS289F5rial port returns to the command mode, where itwaits for a new command to be issued. The singleconversion mode will take l

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CS5531/32/33/34-ASDS289F5 352.6.3. Examples of Using CSRs to Perform Conversions and CalibrationsAny time a calibration or conversion command isissue

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CS5531/32/33/34-AS36 DS289F5offset calibration on physical channel 2 and SDOfalls to indicate that the calibration is complete. Toperform additional c

Página 31

CS5531/32/33/34-ASDS289F5 372.8.1. Conversion Data Output DescriptionsCS5531/33 (16-BIT CONVERSIONS)CS5532/34 (24-BIT CONVERSIONS) Conversion Data Bi

Página 32

CS5531/32/33/34-AS38 DS289F52.9. Digital FilterThe CS5531/32/33/34 have linear phase digital fil-ters which are programmed to achieve a range ofoutpu

Página 33

CS5531/32/33/34-ASDS289F5 392.10. Clock GeneratorThe CS5531/32/33/34 include an on-chip invertingamplifier which can be connected with an externalcry

Página 34

CS5531/32/33/34-AS4 DS289F51. CHARACTERISTICS AND SPECIFICATIONSANALOG CHARACTERISTICS (VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCL

Página 35

CS5531/32/33/34-AS40 DS289F5tation amplifier used on these gain ranges achieveslower noise. OSC2VD+VA+VREF+VREF-DGNDVA -AIN1+SDISCLKS

Página 36

CS5531/32/33/34-ASDS289F5 41OSC2VD+VA+VREF+VREF-DGNDVA -AIN1+SDISCLKSDOCS5532OSC1CS+2.5 VAnalogSupply0.1 µF0.1 µF+-17312AIN1-51591013111214166Optional

Página 37

CS5531/32/33/34-AS42 DS289F5OSC2VD+VA+VREF+VREF-DGNDVA -AIN1+SDISCLKSDOCS5532OSC1CS10Ω+3 VAnalogSupply0.1 µF0.1 µF17312AIN1-51591013111214166OptionalC

Página 38

CS5531/32/33/34-ASDS289F5 432.12. Getting StartedThis A/D converter has several features. From asoftware programmer’s prospective, what shouldbe done

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CS5531/32/33/34-AS44 DS289F53. PIN DESCRIPTIONS Clock GeneratorOSC1; OSC2 - Master Clock.An inverting amplifier inside the chip is connected between

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CS5531/32/33/34-ASDS289F5 45SDI - Serial Data Input.SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK. SD

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CS5531/32/33/34-AS46 DS289F54. SPECIFICATION DEFINITIONSLinearity ErrorThe deviation of a code from a straight line which connects the two endpoints

Página 42

CS5531/32/33/34-ASDS289F5 475. ORDERING INFORMATION6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as

Página 43

CS5531/32/33/34-AS48 DS289F57. PACKAGE DRAWINGSNotes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do inc

Página 44

CS5531/32/33/34-ASDS289F5 49Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch a

Página 45

CS5531/32/33/34-ASDS289F5 5ANALOG CHARACTERISTICS (Continued) (See Notes 1 and 2.) Notes: 5. The voltage on the analog inputs is amplified by the PGI

Página 46

CS5531/32/33/34-AS50 DS289F5RevisionsREVISION DATE CHANGESPP1 Jan 1999 Initial releasePP6 Sep 2004 Added lead-free devicesF1 Jul 2005 Updated with mos

Página 47

CS5531/32/33/34-AS6 DS289F5ANALOG CHARACTERISTICS (Continued) (See Notes 1 and 2.)8. All outputs unloaded. All input CMOS levels.9. Power is specifie

Página 48

CS5531/32/33/34-ASDS289F5 7TYPICAL RMS NOISE (nV), CS5531/32/33/34 (See notes 11, 12 and 13)Notes: 11. Wideband noise aliased into the baseband. Refer

Página 49

CS5531/32/33/34-AS8 DS289F55 V DIGITAL CHARACTERISTICS (VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V;See Notes 2 and 16.)3 V DIGITAL CHARACTERISTICS (TA = 25 °

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CS5531/32/33/34-ASDS289F5 9DYNAMIC CHARACTERISTICS 17. The ADCs use a Sinc5 filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc5 fi

Modelos relacionados CS5533-AS | CS5532-AS | CS5531-AS |

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