Cirrus-logic CS4392 Manual do Utilizador descarregar pdf (Página 35)

CS4392

DS459PP3 35

SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: logic 0 = AGND,

logic 1 = VL)

Notes: 7. t

spi

only needed before first falling edge of CS after RST rising edge. t

spi

= 0 at all other times.

8. Data must be held for sufficient time to bridge the transition time of CCLK.

9. For F

SCK

< 1 MHz

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency f

sclk

-6MHz

RST

Rising Edge to CS Falling t

srs

500 - ns

CCLK Edge to CS

Falling (Note 7) t

spi

500 - ns

High Time Between Transmissions t

csh

1.0 - µs

Falling to CCLK Edge t

css

20 - ns

CCLK Low Time t

scl

82 - ns

CCLK High Time t

sch

82 - ns

CDIN to CCLK Rising Setup Time t

dsu

40 - ns

CCLK Rising to DATA Hold Time (Note 8) t

15 - ns

Rise Time of CCLK and CDIN (Note 9) t

-100ns

Fall Time of CCLK and CDIN (Note 9) t

-100ns

dsu

sch

scl

CCLK

CDIN

css

csh

spi

srs

RST

Figure 39. SPI Control Port Timing

1 2 ... 30 31 32 33 34 35 36 37 38 39 40

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