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Optimizing the Performance of CS553x ADCs

1. INTRODUCTION

Getting optimum performance with high-performance converters is not a trivial task. Good system grounding tech-

niques, power supply filtering, careful board layout, and control of system clocks and high-speed digital signals is of

utmost importance. We will cover these and other subjects in this application note in order to allow your design to

get the best performance from the CS5531/2/3/4 converters.

The CS5531/2/3/4 family of Delta-Sigma converters are some of the lowest-noise DC measurement devices in the

market. These devices are suitable for many applications where high-resolution measurements of very small DC

voltages are required, such as weigh scales, pressure transducers, and thermocouples. With a built in, low-noise,

programmable gain amplifier, the full-scale input range can be as low as 39.0625 mV DC in unipolar mode with a

2.5 V or 5 V VREF. As will be demonstrated in this application note, the input scale can be reduced even further,

allowing very small differential inputs to be measured to a high degree of resolution. For example, as explained in

this document, a 10 mV full-scale unipolar input can be measured to 0.596 nV per least-significant bit with the 24-

bit devices. Obviously the output will contain noise, but with software averaging, that noise can be resolved to an

impressive number of noise-free bits.

2. THE IMPORTANCE OF A GOOD GROUND PLANE

In order to reduce board costs, some designs may attempt to use single- or double-sided boards and fill unrouted

areas with a ground plane. Please be aware that this is not an effective practice in a high-performance analog-to-

digital conversion circuit. A low-noise, low-impedance, uninterrupted ground plane is extremely important in order

to get optimum performance from the ADC. However, filling unused areas around the input traces with copper and

connecting that copper to the ground plane does have some additional advantages regarding Faraday shielding.

The ground plane is the point of reference for many signals on the board. The extremely low-level analog input sig-

nals are very susceptible to corruption from noise voltage transients on the ground plane. Since the ground plane is

used to conduct supply and return currents for high-speed signals, it is possible to introduce unwanted noise voltage

drops across the ground plane.

Consider the best possible PCB layout for the simple schematic shown in Figure 1 below.

Figure 1. Analog Input Circuit for a CS5534 ADC

AIN+

AIN-

VA+

VA-

CS5534

V+

AIN+

AIN-

C1C2 C4

AN299

SEP ‘06

AN299REV1

1 2 3 4 5 6 7 8 9 10

Resumo do Conteúdo

Página 1 - 1. INTRODUCTION

Página 2 - the digital ground (DGND)

10 AN299REV1AN2998. REVISION HISTORYRelease Date ChangesREV1 SEP 2006 Initial ReleaseContacting Cirrus Logic SupportFor all product questions and inqu

Página 3 - Loop antenna effect

2 AN299REV1AN299Figure 2. Preferred Layout for Minimizing Differential Noise from the Ground PlaneAs illustrated in Figure 2, if a high-speed signal

Página 4 - 4 AN299REV1

AN299REV1 3AN299Figure 3. Antenna Loop Caused by Ground or Power Plane SplitsIt is important to note that the CS5531/2/3/4 devices do not have an AGN

Página 5 - 5. OPTIMIZING THE INPUT SPAN

4 AN299REV1AN299power pins. The practice of placing the bypass capacitors on the opposite side of the circuit board and connectingthem to the power pi

Página 6 - 6. DC MEASUREMENT AVERAGING

AN299REV1 5AN299Figure 4. Ferrite Bead and X7R Ceramic Capacitor Impedance vs. Frequency4. CONTROLLING DIGITAL SIGNAL NOISEThe ADC is a mixed-signal

Página 7 - AN299REV1 7

6 AN299REV1AN29916 (CS5531/3) or 24 (CS5532/4) bits and placed in the output register. At reset the value in all of the offset registersis zero (0x000

Página 8 - 8 AN299REV1

AN299REV1 7AN299magnitude resulting in higher weights for the new reading. See Figure 5 to compare the step responses of thesealgorithms.Figure 5. Al

Página 9 - 7. CONCLUSION

8 AN299REV1AN299-50-40-30-20-10010203040500 200 400 600 800 1000SamplesNormalized Output Code (lsb)051015202530354045506050403020100-10-20-30-40-50-60

Página 10 - 8. REVISION HISTORY

AN299REV1 9AN299In most applications the simple exponential average of 64 would result in excessive output settling latency, so anadaptive algorithm c

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Cirrus-logic AN299 Manual do Utilizador Página 1

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