Copyright © Cirrus Logic, Inc. 2005(All Rights Reserved)http://www.cirrus.comEvaluation Board for CS5368Features! Single-Ended to Differential Analog
10 DS624DB1CDB53684.2 SwitchesThe CDB5368 Evaluation Board switches are used for setting speed modes and format protocols and forresetting devices to
DS624DB1 11CDB53684.5 Power Supply CircuitryPower is applied to the evaluation board through five binding posts (+5 V, +12 V, -12 V, VA and GND). TheG
12 DS624DB1CDB53685. SCHEMATICS Figure 4. CS5368 (Schematic page 1)
DS624DB1 13CDB5368 Figure 5. Clock Generation (Schematic page 2)
14 DS624DB1CDB5368 Figure 6. FPGA (Schematic page 3)
DS624DB1 15CDB5368 Figure 7. Control Port (Schematic page 4)
16 DS624DB1CDB5368 Figure 8. Clock and Data Buffers (Schematic page 5)
17 DS624DB1CDB5368 Figure 9. CD8406 S/PDIF Output (Schematic page 6)
DS624DB1 18CDB5368 Figure 10. Analog Inputs 1 to 4 (Schematic page 7)
19 DS624DB1CDB5368 Figure 11. Analog Inputs 5 to 8 (Schematic page 8)
2 DS624DB1CDB5368TABLE OF CONTENTS1. CDB5368 System Overview...
DS624DB1 20CDB5368 Figure 12. Power (Schematic page 9)
21 DS624DB1CDB53686. BOARD LAYOUT AND ROUTING PLOTS Figure 13. Top Silkscreen
22 DS624DB1CDB5368 Figure 14. Top Layer
DS624DB1 23CDB5368 Figure 15. Bottom Layer
24 DS624DB1CDB53687. REVISION HISTORY Release Date ChangesDB1 September 2005 Initial ReleaseContacting Cirrus Logic SupportFor all product questions
DS624DB1 3CDB53681. CDB5368 SYSTEM OVERVIEWThe CDB5368 Evaluation Board provides an excellent means of quickly evaluating the CS5368. A digital audio
4 DS624DB1CDB53683.1.1 S1 and S4 Switch OperationDIP Switch S1 contains six switches that function as described below.M1,M0 set the device Speed Mode
DS624DB1 5CDB53683.2 Control-Port EvaluationThe CDB5368 is shipped with a Cirrus Logic designed Microsoft Windows-based program that allows fullcontro
6 DS624DB1CDB53683.3 FlexGUI Hi-Level ViewThe Cirrus Logic FlexGUI defaults to the Hi-Level View as shown in Figure 1. This view provides functionally
DS624DB1 7CDB53683.4 FlexGUI Low-Level ViewThe Low-level Register Map view provides direct control over the CS5368, the FPGA and GPIO settingsthat cha
8 DS624DB1CDB53683.5 Bit Definitions3.5.1 CS5368 BitsThe Low-Level view of the FlexGUI provides the full register set of the CS5368 under the CS5368 t
DS624DB1 9CDB5368In TDM mode, SDOUT_SEL1 and SDOUT_SEL 0 extract two stereo pairs from the CS5368 TDM stream,convert the data to Left-Justified PCM fo
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