Cirrus-logic CS42L73 Manual do Utilizador

Copyright  Cirrus Logic, Inc. 2013 (All Rights Reserved)http://www.cirrus.comJULY '13DS882F1Ultralow Power Mobile Audio and Telephony CODECProdu

10 DS882F1CS42L73Figure 27.I²S Format ...

100 DS882F1CS42L736.21 Playback Digital Control (Address 19h)6.21.1 Speakerphone [A], Ear Speaker/Speakerphone Line Output [B] (SES) Playback Channels

DS882F1 101CS42L736.21.5 Speakerphone Digital MuteConfigures a digital mute on the volume control for speakerphone, overriding the Speakerphone digita

102 DS882F1CS42L736.23 Speakerphone Out [A] Digital Volume Control (Address 1Ch)6.23.1 Speakerphone Out [A] Digital Volume Control Normally, this cont

DS882F1 103CS42L736.25 Headphone Analog Volume Control: Channel A (Address 1Eh) and B (Address 1Fh)6.25.1 Headphone x Analog MuteConfigures an analog

104 DS882F1CS42L736.26 Line Output Analog Volume Control: Channel A (Address 20h) and B (Address 21h)6.26.1 Line Output x Analog MuteConfigures an ana

DS882F1 105CS42L736.27 Stereo Input Path Advisory Volume (Address 22h)Register is applicable only if ADPTPWR = 000b (Class-H power adapted to volume s

106 DS882F1CS42L736.29 ASP Input Advisory Volume (Address 24h)Register is applicable only if ADPTPWR = 000b (Class-H power adapted to volume setting)

DS882F1 107CS42L736.31 Limiter Attack Rate Headphone/Line Output (HL) (Address 26h)6.31.1 Limiter Attack Rate HLIf limiter attack volume changes are c

108 DS882F1CS42L736.33 Limiter Min/Max Thresholds Headphone/Line Output (HL) (Address 28h)6.33.1 Limiter Maximum Threshold HLSets the maximum level, b

DS882F1 109CS42L736.35 Limiter Control, Release Rate Speakerphone [A] (Address 2Ah)6.35.1 Peak Detect and Limiter Speakerphone [A]Configures the peak

DS882F1 11CS42L73Table 11. Digital Mixer Soft Ramp Rates ...

110 DS882F1CS42L736.36 Limiter Min/Max Thresholds Speakerphone [A] (Address 2Bh)6.36.1 Limiter Maximum Threshold Speakerphone [A]Sets the maximum leve

DS882F1 111CS42L736.37 Limiter Attack Rate Ear Speaker/Speakerphone Line Output (ESL) [B](Address 2Ch)6.37.1 Limiter Attack Rate ESL [B]If limiter att

112 DS882F1CS42L736.39 Limiter Min/Max Thresholds Ear Speaker/Speakerphone Line Output (ESL) [B](Address 2Eh)6.39.1 Limiter Maximum Threshold ESL [B]S

DS882F1 113CS42L736.40 ALC Enable and Attack Rate AB (Address 2Fh)6.40.1 ALC for Channels A and B (ALCx)Enables ALC independently for channels A and B

114 DS882F1CS42L736.42 ALC Threshold AB (Address 31h)6.42.1 ALC Maximum Threshold for Channels A and BSets the maximum level, below full scale, at whi

DS882F1 115CS42L736.43 Noise Gate Control AB (Address 32h)6.43.1 Noise Gate Enable for Channels A and B (NGx)Enables noise gating independently for ch

116 DS882F1CS42L736.44 ALC and Noise Gate Misc Control (Address 33h)6.44.1 ALC Ganging of Channels A and BConfigures whether ALC for channels A and B

DS882F1 117CS42L736.45 Mixer Control (Address 34h) 6.45.1 VSP Mixer Output StereoSelects which of the following mixer outputs is sent to the VSP outpu

118 DS882F1CS42L736.46 Stereo Mixer Input Attenuation (Addresses 35h through 54h)Sets the level of attenuation to be applied to various stereo digital

DS882F1 119CS42L736.46.1 Stereo Mixer Input Attenuation4BhASP Left Mixer:VSP Mono AttenuationAudio Serial Port (ASP)Left(A)Voice Serial Port(VSP)Mono(

12 DS882F1CS42L731. PACKAGE PIN/BALL ASSIGNMENTS AND CONFIGURATIONS1.1 64-Ball Wafer-Level Chip Scale Package (WLCSP)Top-Down(Though Package)ViewH5SPK

120 DS882F1CS42L736.47 Mono Mixer Controls (Address 55h)6.47.1 Speakerphone (SPK) Mixer, ASP SelectSelects the input to ASP input attenuator of the SP

DS882F1 121CS42L736.48 Mono Mixer Input Attenuation (Addresses 56h through 5Dh)Sets the level of attenuation to be applied to various mono digital mix

122 DS882F1CS42L736.49 Interrupt Mask Register 1 (Address 5Eh)The bits of this register serve as a mask for the interrupt sources found in Interrupt S

DS882F1 123CS42L736.51.3 Digital Mixer Overflow- Read Only; sticky;  edge can trigger interruptIndicates the over-range status in the digital mixer d

124 DS882F1CS42L736.52.3 Audio ASRC Data Out Lock- Read Only; sticky;  edge can trigger interruptIndicates the lock status of the ASRC for the audio

DS882F1 125CS42L736.53 Fast Mode 1 (Address 7Eh)6.53.1 Fast Mode Bits 15:8See “Fast Start Mode” on page 73. 6.54 Fast Mode 2 (Address 7Fh)6.54.1 Fast

126 DS882F1CS42L738. PERFORMANCE DATANote, unless otherwise noted, the data/plots in this section are for nominal supply voltages (VA = VCP = VL = 1.8

DS882F1 127CS42L738.2 Analog Mic/Line ADC and Digital Mic Input Path Attributes8.2.1 Input Path Digital LPF Response-6 -4 -2 0 2 4 6 8 10 12-6-4-20246

128 DS882F1CS42L738.2.2 Input Path Digital HPF Response0.4 0.45 0.5 0.55 0.6 0.65−100−90−80−70−60−50−40−30−20−100Frequency (normalized to Fs)Magnitude

DS882F1 129CS42L738.3 Core Circuitry Attributes8.3.1 ASRC Attributes8.3.1.1 ResponseThe following curves illustrate the ASRC frequency response. The h

DS882F1 13CS42L731.2 65-Ball Fine-Pitch Ball Grid Array (FBGA) PackageTop-Down(Though Package)ViewH5SPKLINEO-ASP_LRCKDMIC_SDB5VLA5VSP_SDINH6MIC1_BIASM

130 DS882F1CS42L738.3.1.2 Group DelayThe group-delay equations for the ASRCs are specified in “ASRC Digital Filter Characteristics” onpage 25. The fol

DS882F1 131CS42L738.4 Analog Output Paths Attributes8.4.1 DAC Digital LPF Response0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1−100−90−80−70−60−50−40−30−20−

132 DS882F1CS42L738.4.2 DAC HPF Response8.4.3 Output Analog Volume Nonlinearity (DNL and INL)0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2x 10−3−3.5−3−2.5−2−1

DS882F1 133CS42L738.4.4 Startup TimesTable 16 lists the startup times for the analog output paths. For each case, the device has been previouslyconfig

134 DS882F1CS42L739. PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over t

DS882F1 135CS42L7310.PACKAGE DIMENSIONS10.1 WLCSP Package64-Ball WLCSP (3.44 x 3.44 mm Body) Package Drawing Table 17. WLCSP Package DimensionsDimensi

136 DS882F1CS42L7310.2 FBGA Package65-Ball FBGA (5 x 5 mm Body) Package Drawing Table 18. FBGA Package DimensionsDimensionMillimetersMinimum Nominal M

DS882F1 137CS42L7311.THERMAL CHARACTERISTICSNotes:1. Test printed circuit-board assembly (PCBA) constructed in accordance with JEDEC standard JESD51-9

138 DS882F1CS42L7314.REVISION HISTORYRevision ChangesF1 • Removed all references to PDN_LDO. • Updated Stereo DAC to Headphone Amplifier: High HP powe

DS882F1 139CS42L73Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nea

14 DS882F1CS42L731.3 Pin/Ball DescriptionsName Location DescriptionWLCSP FBGAMCLK1MCLK2A6D6B3B2High Speed Clock (Input). Potential clock sources for t

DS882F1 15CS42L73LINEOUTALINEOUTBF6F5G2F2Line Audio Output (Output). The full-scale output level is specified in the Line Output Characteristics speci

16 DS882F1CS42L731.4 Digital Pin/Ball I/O ConfigurationsNotes:• All outputs are disabled when RESET is active.• Internal weak pull up/down minimum and

DS882F1 17CS42L732. TYPICAL CONNECTION DIAGRAMNote 13OptionalBias Res.Note 9Note 4DGNDVLSCLSDARPASP_LRCKApplications ProcessorASP_SCLKASP_SDINASP_SDOU

18 DS882F1CS42L732.1 Low-Profile Charge-Pump CapacitorsThe “Typical Connection Diagram” on page 17 shows that the recommended capacitor values for the

DS882F1 19CS42L733. CHARACTERISTIC AND SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSTest Conditions: GND = AGND = PGND = CPGND = DGND = 0 V; all volt

2 DS882F1CS42L73Stereo Analog-to-Digital Features 91-db dynamic range (A-weighted) -85 dB THD+N  Independent ADC channel control 2:1 stereo analog

20 DS882F1CS42L73ABSOLUTE MAXIMUM RATINGSTest Conditions: GND = AGND = PGND = CPGND = DGND = 0 V; all voltages are with respect to ground (GND).WARNIN

DS882F1 21CS42L73DC ELECTRICAL CHARACTERISTICSTest Conditions: Connections to the CS42L73 are shown in the “Typical Connection Diagram” on page 17; GN

22 DS882F1CS42L73ANALOG INPUT TO SERIAL PORT CHARACTERISTICS Test Conditions (unless otherwise specified): Connections to the CS42L73 are shown in the

DS882F1 23CS42L73Notes:10. Fs is the sampling frequency used by the core and the A/D and D/A converters. For specifications, a default value of 48kHz

24 DS882F1CS42L73STEREO-ADC AND DUAL-DIGITAL-MIC DIGITAL FILTER CHARACTERISTICSTest Conditions (unless otherwise specified): Fs = 48 kHz (Note 10), fD

DS882F1 25CS42L73THERMAL OVERLOAD DETECT CHARACTERISTICSTest Conditions: Connections to the CS42L73 are shown in the “Typical Connection Diagram” on p

26 DS882F1CS42L73MIC BIAS CHARACTERISTICSTest Conditions (unless otherwise specified): Connections to the CS42L73 are shown in the “Typical Connection

DS882F1 27CS42L73SERIAL PORT TO STEREO HP OUTPUT CHARACTERISTICSTest conditions (unless otherwise specified): “Typical Connection Diagram” on page 17

28 DS882F1CS42L73Notes:30. Analog Gain setting (refer to “Headphone x Analog Volume Control” on page 103 or “Line Output x Analog Volume Con-trol” on

DS882F1 29CS42L73SERIAL PORT TO STEREO LINE OUTPUT CHARACTERISTICSTest conditions (unless otherwise specified): Connections to the CS42L73 are shown i

DS882F1 3CS42L73General DescriptionThe CS42L73 is a highly integrated, low-power, audio and telephony CODEC for portable applications such assmartphon

30 DS882F1CS42L73SERIAL PORT TO MONO EAR SPEAKER OUTPUT CHARACTERISTICSTest conditions (unless otherwise specified): Connections to the CS42L73 are sh

DS882F1 31CS42L73SERIAL PORT-TO-MONO SPEAKERPHONE OUTPUT CHARACTERISTICSTest conditions (unless otherwise specified): “Typical Connection Diagram” on

32 DS882F1CS42L73SERIAL PORT TO MONO SPEAKERPHONE LINE OUTPUT CHARACTERISTICSTest conditions (unless otherwise specified): Connections to the CS42L73

DS882F1 33CS42L73STEREO/MONO DAC INTERPOLATION AND ON-CHIP DIGITAL/ANALOG FILTER CHARACTERISTICSTest Conditions (unless otherwise specified): Fs = 48

34 DS882F1CS42L73POWER CONSUMPTION Test conditions (unless otherwise specified): Connections to the CS42L73 are shown in the “Typical Connection Diag

DS882F1 35CS42L73DIGITAL INTERFACE SPECIFICATIONS AND CHARACTERISTICSTest Conditions (unless otherwise specified): Connections to the CS42L73 are show

36 DS882F1CS42L73SWITCHING SPECIFICATIONS—POWER, RESET, AND MASTER CLOCKSTest conditions (unless otherwise specified): Connections to the CS42L73 are

DS882F1 37CS42L73SWITCHING SPECIFICATIONS—DIGITAL MIC INTERFACETest conditions: Inputs: Logic 0 = GND = DGND = 0 V, Logic 1 = VL; TA = +25 C; CLOAD =

38 DS882F1CS42L73SWITCHING SPECIFICATIONS—SERIAL PORTS—I²S FORMATTest conditions: Inputs: Logic 0 = GND = DGND = 0 V, Logic 1 = VL; TA = +25 C; x = X

DS882F1 39CS42L73SWITCHING SPECIFICATIONS—SERIAL PORTS—PCM FORMATTest condition: Inputs: Logic 0 = GND = DGND = 0 V, Logic 1 = VL; TA = +25 C; x = X

4 DS882F1CS42L73TABLE OF CONTENTS1. PACKAGE PIN/BALL ASSIGNMENTS AND CONFIGURATIONS ... 121.1 64-Bal

40 DS882F1CS42L73SWITCHING SPECIFICATIONS—CONTROL PORTTest conditions: Inputs: Logic 0 = GND = DGND = 0 V, Logic 1 = VL; TA = +25 C; SDA load capacit

DS882F1 41CS42L734. APPLICATIONS4.1 Overview4.1.1 Basic ArchitectureThe CS42L73 is a highly integrated, ultralow power, 24-bit audio CODEC comprising

42 DS882F1CS42L734.2 Internal Master Clock GenerationTable 1 outlines the supported internal Master Clock (MCLK) nominal frequencies and how they are

DS882F1 43CS42L734.4 Pseudodifferential OutputsThe CS42L73 provides access to the headphone and line output amplifiers’ reference inputs via theHPOUT_

44 DS882F1CS42L734.5 Class H Amplifier The CS42L73 headphone and line output amplifiers use a patent-pending Cirrus Logic Tri-Modal Class Htechnology

DS882F1 45CS42L734.5.1.1 Standard Class AB Operation (Mode 001, 010, and 011)When the ADPTPWR is set to 001, 010, or 011, the rail voltages supplied t

46 DS882F1CS42L734.5.1.3 Adapt-to-Output Signal (Mode 111)If the Adaptive Power bits are set to 111, the CS42L73 determines which of the three sets of

DS882F1 47CS42L73When the charge pump transitions from the higher set of rail voltages to the lower set, there is a 2-seconddelay before the charge pu

48 DS882F1CS42L73Output Level-15 dB+VCP2 secondsAmplifier Rail VoltageTimeTime+VCP2+VCP32 seconds-VCP-VCP2-VCP3-11 dBFigure 20. VCP_FILT Hysteresis

DS882F1 49CS42L734.5.3 EfficiencyAs discussed in previous sections, the HPOUTx and LINEOUTx amplifiers may operate from one of threepairs of rail volt

DS882F1 5CS42L734.11.2 Mixer Input Attenuation Adjustment ... 634.11

50 DS882F1CS42L73maximum threshold. When the input signal level falls below the maximum threshold, the AOUT volume re-turns to its original level set

DS882F1 51CS42L734.7 Analog Output Current LimiterThe CS42L73 features built-in current-limit protection for both the headphone and line output amplif

52 DS882F1CS42L73• Toggles at external sample rate (Fsext)• xSP_SDIN Serial data input• xSP_SDOUT Serial data output4.8.3 High-impedance ModeThe seria

DS882F1 53CS42L73The master mode supported rates for each supported MCLK are listed in the aforementioned table. Thetable also documents how to progra

54 DS882F1CS42L73 4.8.6 FormatsTable 7 lists formats supported on the CS42L73 serial ports: The XSPDIF and VSPDIF register bits are used to select the

DS882F1 55CS42L734.8.6.1 I²S FormatSelecting I²S format provides the following behavior:• Up to 24 bits/sample of stereo data can be transported (see

56 DS882F1CS42L73Mode 1:– WA may be one or up to all-but-one xSP_SCLK periods wide– 1st data bit is aligned to WAMode 2:– WA may be one xSP_SCLK perio

DS882F1 57CS42L734.8.7 Mono/StereoStereo/mono conversion is required whenever the number of channels for a serial port interface formatdoes not match

58 DS882F1CS42L73The CS42L73 will always transmit 24-bit-deep data if at least 24 serial clocks are present per channelsample. If less than 24 serial

DS882F1 59CS42L734.9 Asynchronous Sample Rate Converters (ASRCs)The CS42L73 uses ASRCs to bridge potentially different sample rates at the serial port

6 DS882F1CS42L736.8.4 Short Detect Automatic Mute Control ... 866.9 D

60 DS882F1CS42L734.10.2 Digital Microphone (DMIC) InterfaceThe DMIC Interface can be used to collect Pulse Density Modulation (PDM) audio data from th

DS882F1 61CS42L734.10.2.4 DMIC Interface Clock GenerationTable 10 outlines the supported DMIC Interface Serial Clock (DMIC_SCLK) nominal frequencies a

62 DS882F1CS42L73012Attenuation+Attenuation3012Attenuation3+AttenuationAttenuationAttenuationAttenuationAttenuation012Attenuation+Attenuation3012Att

DS882F1 63CS42L734.11.1 Mono and Stereo PathsNotice how Figure 32 distinguishes between stereo and mono channels; there are buses for the stereoinputs

64 DS882F1CS42L734.11.3 Powered-Down Mixer InputsIf an input to the digital mixer is powered down (refer to register controls “Power Control 1 (Addres

DS882F1 65CS42L734.11.5 Mixer Attenuation ValuesThe digital mixer contains fixed attenuation blocks and programmable attenuation blocks. The attenuati

66 DS882F1CS42L73signal may be applied any time during the power-up sequence. If an MCLK signal is present whenRESET is brought high, it is recommende

DS882F1 67CS42L73in “Audio ASRC Data In Lock” on page 124.12. Start transmission of audio data to device.13. Ramp up audio output.• Unmute the analog

68 DS882F1CS42L731. The CS42L73 must be put into a powered down state using the procedure in section “Power-Down Sequence (xSP to HP/LO)” on page 67.2

DS882F1 69CS42L734.13 Using MIC2_SDET as Headphone Plug DetectAlthough the CS42L73 does not have a dedicated headphone plug detect pin, the MIC2_SDET

DS882F1 7CS42L736.21 Playback Digital Control (Address 19h) ... 100

70 DS882F1CS42L734.14 Headphone Plug Detect and Mic Short DetectTo implement “headphone plug detect,” a suitable jack and system GPIO are required. Fi

DS882F1 71CS42L73terrupt Status Register 2 (Address 61h)” on page 123) that are desired to cause an interrupt. The interruptpin is either rising-edge

72 DS882F1CS42L73The first byte sent to the CS42L73 after a Start condition consists of a 7-bit chip address field and a R/Wbit (high for a read, low

DS882F1 73CS42L73If a read address different from that which is based on the last received MAP address is desired, an abort-ed write operation can be

74 DS882F1CS42L73To use fast start mode, a set of registers must be written in a certain sequence. To enable fast start mode,perform the following seq

DS882F1 75CS42L734.18 Headphone High-Impedance ModeDuring normal operation, the headphone output pins are driven by the CS42L73 with low impedance dri

76 DS882F1CS42L735. REGISTER QUICK REFERENCE(Default values are shown below the bit names) I²C Address: 1001010[R/W]—10010100 = 0x94(Write); 10010101

DS882F1 77CS42L7315hMic 1 [A] Pre-Amp, PGAA Vol. Reserved MIC_PREAMPAPGAAVOL5 PGAAVOL4 PGAAVOL3 PGAAVOL2 PGAAVOL1 PGAAVOL0p980000000016hMic 2 [B] Pre-

78 DS882F1CS42L732BhLimiter Thresh-olds Speaker-phone [A]. LMAXSPK2 LMAXSPK1 LMAXSPK0 CUSHSPK2 CUSHSPK1 CUSHSPK0 Reserved Reservedp110000000002ChLimit

DS882F1 79CS42L7340hXSP Rt. Mixer: XSP Right Attenuation. Reserved Reserved XSPB_XSPB_A5XSPB_XSPB_A4XSPB_XSPB_A3XSPB_XSPB_A2XSPB_XSPB_A1XSPB_XSPB_A0p

8 DS882F1CS42L736.39.1 Limiter Maximum Threshold ESL [B] ... 1126.39.2 L

80 DS882F1CS42L7354hVSP Rt. Mixer: VSP Mono Attenuation. Reserved Reserved VSPB_VSPM_A5VSPB_VSPM_A4VSPB_VSPM_A3VSPB_VSPM_A2VSPB_VSPM_A1VSPB_VSPM_A0p11

DS882F1 81CS42L736. REGISTER DESCRIPTION Registers are read/write except for chip ID, revision, and status registers, which are read only. The followi

82 DS882F1CS42L736.4 Power Control 1 (Address 06h)6.4.1 Power Down ADC x Configures the power state of ADC channel x. All the analog front-end circuit

DS882F1 83CS42L736.5 Power Control 2 (Address 07h)6.5.1 Power Down MICx BiasConfigures the power state of the mic bias output.6.5.2 Power Down VSPConf

84 DS882F1CS42L736.6 Power Control 3 and Thermal Overload Threshold Control (Address 08h)6.6.1 Thermal Overload Threshold SettingsConfigures the thres

DS882F1 85CS42L736.6.6 Power Down Line OutputConfigures the Output Driver power state. If the Line Output Driver or Headphone Driver is powered up,the

86 DS882F1CS42L736.8 Output Load, Mic Bias, and MIC2 Short Detect Configuration (Address 0Ah)6.8.1 VP Supply Minimum Voltage SettingConfigures the mic

DS882F1 87CS42L736.9 Digital Mic and Master Clock Control (Address 0Bh)6.9.1 Digital Mic Shift Clock Divide RatioSets the divide ratio between the int

88 DS882F1CS42L736.10 XSP Control (Address 0Ch)6.10.1 Tristate XSP InterfaceDetermines the state of the XSP drivers. Note: Slave/Master Mode is deter

DS882F1 89CS42L736.11 XSP Master Mode Clocking Control (Address 0Dh)Refer to XSP Master Mode Clocking relevant control bits “XSP SCLK Source Equals MC

DS882F1 9CS42L737.3 Layout With Fine-Pitch, Ball-Grid Packages ... 1258.

90 DS882F1CS42L736.12.2 ASP Sample RateIdentifies the ASP audio sample rate.6.12.3 ASP SCLK Source Equals MCLKApplicable only if A_M/S = 1b (Master Mo

DS882F1 91CS42L736.14 VSP Control (Address 10h)6.14.1 Tristate VSP InterfaceDetermines the state of the VSP drivers. Note: Slave/Master Mode is deter

92 DS882F1CS42L736.14.5 VSP SDIN LocationApplicable only if VSPDIF = 0b (I²S Format). Indicates if the received mono data is in the left or right por-

DS882F1 93CS42L736.16 VSP and XSP Sample Rate (Address 12h)6.16.1 VSP Sample RateIdentifies the VSP audio sample rate.6.16.2 XSP Sample RateIdentifies

94 DS882F1CS42L736.17 Miscellaneous Input and Output Path Control (Address 13h)6.17.1 Digital Swap/MonoConfigures transformations on the Input Path A

DS882F1 95CS42L736.17.4 PGA Soft-RampConfigures an incremental volume ramp from the current level to the new level at the specified rate. If PGASoft-R

96 DS882F1CS42L73page 96). If soft-ramping is disabled, a single volume change will occur according to thevolume control change. If soft ramping is en

DS882F1 97CS42L736.18 ADC/Input Path Control (Address 14h)6.18.1 PGA x Input SelectSelects the specified analog input signal into channel x’s PGA. Not

98 DS882F1CS42L736.19 Mic PreAmp and PGA Volume Control: Channel A (Mic 1, Address 15h) and Channel B (Mic 2, Address 16h)6.19.1 Mic PREAMP x VolumeSe

DS882F1 99CS42L736.20 Input Path x Digital Volume Control: Channel A (Address 17h) and B (Address 18h)6.20.1 Input Path x Digital Volume ControlNormal