Cirrus-logic CS8421 Manual do Utilizador descarregar pdf (Página 13)

DS641F6 13

CS8421CS8421

6. After powering up the CS8421, RST should be held low until the power supplies and clocks are settled.

7. The maximum possible sample rate is XTI/128.

8. OLRCK must remain high for at least 8 OSCLK periods in TDM Mode.

9. Only the input or the output serial port can be set as master at a given time.

Master Mode (Note 9)

I/OSCLK Frequency (non-TDM) 64*Fsi/o MHz

OSCLK Frequency (TDM) 256*Fso MHz

I/OLRCK Duty Cycle 45 55 %

I/OSCLK Duty Cycle 45 55 %

I/OSCLK Falling Edge to I/OLRCK Edge t

lcks

-5ns

OSCLK Falling Edge to OLRCK Edge (TDM) t

fss

-5ns

OSCLK Falling Edge to SDOUT Output Valid t

dpd

-7ns

SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge t

3-ns

SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge t

5-ns

Parameters Symbol Min Max Units

OLRCK

(input)

sckh

sckl

fsh

fss

OSCLK

(input)

TDM_IN

(input)

SDOUT

(output)

MSB

dpd

MSB-1

MSB

MSB-1

lrckh

MSB

dpd

MSB-1

I/OLRCK

(input)

I/OSCLK

(input)

SDIN

(input)

SDOUT

(output)

MSB

MSB-1

sckh

sckl

lcks

lckd

Figure 1. Non-TDM Slave Mode Timing Figure 2. TDM Slave Mode Timing

OLRCK

(output)

dpd

fss

OSCLK

(output)

TDM_IN

(input)

SDOUT

(output)

MSB

MSB-1

MSB

MSB-1

MSB

dpd

MSB-1

lcks

I/OLRCK

(output)

I/OSCLK

(output)

SDIN

(input)

SDOUT

(output)

MSB

MSB-1

Figure 3. Non-TDM Master Mode Timing Figure 4. TDM Master Mode Timing

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 34 35

Comentários a estes Manuais

Sem comentários

Cirrus-logic CS8421 Manual do Utilizador Página 13

Comentários a estes Manuais

Manuais e produtos relacionados com Hardware Cirrus-logic CS8421